Cadence's 'Catena' rolls layout optimizer

SANTA CRUZ, Calif. — Harvesting the first fruits from its secretive Catena development project, Cadence Design Systems this week is rolling out Chip Optimizer, a post-route interconnect optimization tool that claims to improve both performance and manufacturability.

Catena, described by Cadence as an "incubation" R&D program, came to light in one of Cadence's analyst conference calls last year. Launched in 2002, Catena now includes around 35 people working in a semi-autonomous environment that's said to parallel a Silicon Valley startup.

The starting point for Chip Optimizer was the "shape-based" routing technology developed by Cooper and Chyan Technologies before its acquisition by Cadence. The Catena effort extended that shape-based technology to handle the speed and capacity challenges of sub-100 nm design, said Richard Brashears, corporate vice president of advanced technology development and head of Catena.

Chip Optimizer, however, is not a router — it's a post-route tool that uses shape-based techniques to perform a variety of via and wire optimizations in order to enhance performance and manufacturability. "I think it's very unique with respect to the combination of manufacturing optimization capabilities with electrical design closure and automation," Brashears said.

To find the best improvements, Chip Optimizer makes use of analysis engines for extraction, timing, signal integrity, and critical area. This technology comes from Cadence's Encounter product line. However, Chip Optimizer is a standalone product that can work with any vendor's place and route tools, Brashears said. He noted that it also works with Cadence's full-custom Virtuoso environment.

Brashears said Chip Optimizer can improve chip performance by 10 to 20 percent, and improve yields as well. This is accomplished through via and wire optimizations such as removal of selected vias in order to conform with recommended design rules.

"At sub-100 nm nodes, there are more sophisticated rules about how vias need to sit within layers of metal that surround them," Brashears said. "With Chip Optimizer, we're able to have a set of constraints that go beyond design rule checking (DRC) to find locations for each of the vias in the metal."

Chip Optimizer can also move wires around, but it's not a geometrically-driven wire spreading tool, Brashears noted. "This is really driven by manufacturing and electrical analysis, so the final location of the interconnect is actually better," he said.

Chip Optimizer is built on the OpenAccess database, and can work with hierarchical or flat designs. Input includes LEF and DEF layout files, Verilog, timing and power constraints, and recommended manufacturing rules. The tool can run automatically or be guided by the user. The output, said Brashears, is simply "the same design with better interconnect."

Chip Optimizer is available immediately. Cadence has not released pricing information.