"Verification today takes 60 to 70 percent of the overall effort, and management always asks if we're getting our money's worth," said Benny Chang, vice president of engineering at Tundra Semiconductor Corp. "Chips are used in ways we can't even imagine. To cover all the operating parameters is not even possible."

Chang said that the cost of a post-silicon "test escape" is much higher than the cost of finding a bug before going to silicon. To maximize verification ROI, he said, it's mandatory to formulate a process that reduces the "lifetime" of bugs, and to build in more design quality in order to reduce the amount of bugs found by the verification team.

Nader Vesseghi, director of engineering for advanced routing at Cisco Systems, noted three types of bugs. These include those for which there's a software workaround, those that impact system performance in a minor way, and "showstoppers" that require silicon respins. It's the latter category that has a huge impact on schedules.

There's no 100 percent verification, Vesseghi said, but designers can move in that direction by using advanced tools, leveraging verification reuse, doing up-front planning, and using multi-disciplinary teams. Vesseghi noted that there are "planning" and "execution" phases of the design cycle, and that shortening planning in order to get to execution quickly results in a longer overall schedule and lower quality coverage.

"Tools play a role in execution, but planning is more of a manual effort," Vesseghi said. "This is an area for further exploration."

"Perfect verification is not possible, and you will see bug escapes, so where do we best invest?" asked Wolfgang Roesner, distinguished engineer at IBM's System Technology Group. He suggested two places to focus: improving the "steepness" of the bug finding curve, and reducing the percentage of hard-to-detect bugs that escape to the lab.

It's important to optimize the design methodology for verification, but verification is only one of many design disciplines, Roesner noted. Hierarchical verification is more efficient, but you can't wait until one level of hierarchy finishes to move on to another, he said. And while using different methods improves the bug finding rate, using poorly integrated methods wastes verification investment and efficiency, he said. As a provider of processor intellectual property (IP), MIPS Technologies faces some unique challenges, noted John Bourgoin, MIPS president and CEO. He noted there are millions of ways customers could configure a MIPS processor, and billions of possible system implementations. Yet verifying even a single processor configuration is very complex.

There are several "tiers" for bug finding, Bourgoin said, and the cost goes up by a factor of ten at each tier. At the bottom is model testing, which is the best place to find bugs. Beyond that are component test, system test, and field failures.

"There is almost no tool we won't buy or person we won't hire if we think we will get a material improvement in this [verification] space," Bourgoin said. "The bigger problem is [people] resources versus tools."

One of two EDA vendor representatives on the panel, Kathryn Kranen, president and CEO of Jasper Design Automation, spoke of the "upside" of verification. "What would you do if you could be certain of verification results?" she asked. Her answers included: ensure new features aren't dropped due to inadequate verification, make late-stage specification changes, try bold new architectures, innovate more aggressively, and leapfrog your competition.

Robert Hum, vice president of Mentor Graphics' design verification and test division, spoke of the importance of methodology. He noted that a "testbench centric" methodology has a slight advantage for first-pass success, but if a respin is needed, it's much less likely to succeed. "The methodology you pick has more of an impact than the tools you pick," he said.

Panel moderator Lucio Lanza, managing director of Lanza TechVentures, cautioned against "getting to the moon by climbing a tree." With a billion transistors on a chip within three years, there will have to be "significant change," he said. "Will we continue selling tools, or combine resources and sell solutions?" he asked.