Panelists seek ROI in IC verification

SANTA CLARA, Calif. — You can never design a 100 percent bug-free IC, but you can invest in strategies that will help ensure verification success, according to panelists at the DesignCon 2006 conference here Tuesday (Feb. 7). Panelists were charged with evaluating verification return on investment (ROI) by assessing the business impact of bug escapes.

"Verification today takes 60 to 70 percent of the overall effort, and management always asks if we're getting our money's worth," said Benny Chang, vice president of engineering at Tundra Semiconductor Corp. "Chips are used in ways we can't even imagine. To cover all the operating parameters is not even possible."

Chang said that the cost of a post-silicon "test escape" is much higher than the cost of finding a bug before going to silicon. To maximize verification ROI, he said, it's mandatory to formulate a process that reduces the "lifetime" of bugs, and to build in more design quality in order to reduce the amount of bugs found by the verification team.

Nader Vesseghi, director of engineering for advanced routing at Cisco Systems, noted three types of bugs. These include those for which there's a software workaround, those that impact system performance in a minor way, and "showstoppers" that require silicon respins. It's the latter category that has a huge impact on schedules.

There's no 100 percent verification, Vesseghi said, but designers can move in that direction by using advanced tools, leveraging verification reuse, doing up-front planning, and using multi-disciplinary teams. Vesseghi noted that there are "planning" and "execution" phases of the design cycle, and that shortening planning in order to get to execution quickly results in a longer overall schedule and lower quality coverage.

"Tools play a role in execution, but planning is more of a manual effort," Vesseghi said. "This is an area for further exploration."

"Perfect verification is not possible, and you will see bug escapes, so where do we best invest?" asked Wolfgang Roesner, distinguished engineer at IBM's System Technology Group. He suggested two places to focus: improving the "steepness" of the bug finding curve, and reducing the percentage of hard-to-detect bugs that escape to the lab.

It's important to optimize the design methodology for verification, but verification is only one of many design disciplines, Roesner noted. Hierarchical verification is more efficient, but you can't wait until one level of hierarchy finishes to move on to another, he said. And while using different methods improves the bug finding rate, using poorly integrated methods wastes verification investment and efficiency, he said.