News & Analysis

Sparks fly at Cooley's 'Bigwig' panel

2/23/2006 9:11 PM EST

SAN JOSE, Calif. — Sparks flew at Deepchip.com moderator John Cooley's annual "Bigwigs" panel at the Design & Verification Conference (DVCon) here Thursday (Feb. 23), with representatives from smaller companies suggesting that pricing strategies by the larger companies were hurting the EDA market.

Kathryn Kranen, CEO of Jasper Design Automation, accused Synopsys Inc. and Cadence Design Systems Inc. of giving away software to undercut startups and expand their presence in customers' tool flows.

Mike Gianfagna, CEO of Aprio Technologies expressed concern that EDA vendors would "crater the market" for design-for-manufacturing (DFM) tools by giving away technology. With chip makers spending in the neighborhood of $4 billion on new fabs, Gianfagna argued, DFM technology providers could see some budgets that "may have an extra zero or two" compared to what EDA companies typically see.

"We've been burning the grass for too long," said Gianfagna, who added that, as a former Cadence employee, he has seen some ridiculously low average selling prices of tools. He argued that the EDA industry needs to "stop pricing to budget and start pricing to value," suggesting that companies have set a goal to command as much of customers' tool budgets as possible without determining what is a fair price for the value provided.

Though acknowledging that his company sometimes takes the lead of its larger competitors and cuts the price of its tools to make a sale, Rajeev Madhavan, CEO of Magma Design Automation Inc. said he has more often told salespeople to walk away from deals when he felt they would jeopardize EDA pricing integrity. He pointed out that a smaller percentage of semiconductor industry revenue is being spent on EDA tools than it was a few years ago.

"We shoot ourselves in the foot a little bit," Madhavan said. "We've got to stop doing that eventually." He argued that part of the problem is that EDA has failed to provide customers with the level of automation the semiconductor industry needs.

According to Gary Smith, chief EDA analyst at Gartner Dataquest, because physical implementation tools from Cadence, Synopsys and Magma have all been proven on 65-nm designs which have taped out, customers have been "having a ball playing these guys off each other" in order to lower tool prices. A lot of customers, Smith said, did not use their entire CAD budgets in 2005 because EDA vendors were giving them such great deals.

Smith said, as of the time of the Design Automation Conference last June, Synopsys and Cadence were showing the most willingness to cut prices, with Magma "holding the line well."

Antun Domic, Synopsys' general manager of implementation, said it is a myth that big EDA companies give away tools for free.

"Anyone who has been in EDA sales will tell you, if you offer a customer a tool for free, they will say, 'I don't want that, so give me the other stuff for less,'" Domic said.

Who started the Synopsys-Magma patent dispute?
Madhavan and Domic also voiced a difference opinion over who initiated the high-profile patent litigation dispute between the two companies.

"The idea that we [Magma] started it is absurd," Madhavan said. He acknowledged that lawyers from his company drafted and sent Synopsys a letter warning that Synopsys may be infringing on Magma patents. Madhavan characterized this letter as a typical business practice in EDA and not a litigious act.

Domic dismissed the notion that Magma's letter was "just saying hi," adding, "If you are sending letters claiming that we are violating your patents, we take that very seriously."

When Cooley asked both men whether their companies were even using the patents in question, Madhavan gave an unqualified "no," while Domic refused to answer the question directly.

Madhavan said the Synopsys-Magma lawsuit is costing the two companies a combined $50 million per year — a figure that Domic disputed as being too high. Madhavan said that money could be better spent to employ 400 engineers and develop new technologies and innovation to benefit the industry.

"We as an industry have to stop [the preponderance of litigation between companies]," Madhavan said.

Panelists seem to find common ground on the issue of SystemC adoption, with even representatives of companies whose tools do not support the language agreeing that a transition to electronic system level (ESL) design is taking place.

Brett Cline, vice president of customer operations and services group for Forte Design Systems, said SystemC is experiencing "very strong growth." He said the SystemC community Web site now has more than 35,000 registered users and has chalked up more than 277,000 downloads. He referenced the finding in Cooley's 2005 "verification census" survey that 42 percent of respondents indicated that they were using SystemC — up from 32 percent in 2004. Cline said 26 companies are now on the SystemC committee, including many represented on the panel.

Despite the conventional wisdom, Smith said, the U.S. is moving to electronic system design along with Japan and Europe. The problem, he said, is that of the three different ESL methodologies identified by Gartner Dataquest, only tools for algorithmic methodologies are being made commercially available. The EDA industry is not serving the other two methodologies, processor/memory and control logic, Smith said.

Ted Vucurevich, Cadence senior vice president and chief technology officer for advanced R&D, said SystemC adoption has been a regional issue based on locality. It's no surprise that SystemC adoption started in Japan and Europe, he said, based on the products created in those regions.

Madhavan said SystemC tools have been lacking, but that he certainly believes that the transition to SystemC will happen at some point.

"People doing hardware design at the system level are using SystemC," said Cline, who added that SystemC is not so much a language as library that sits atop C++.

Panelists also seemed to agree that the emergence of SystemC does not doom SystemVerilog.

"SystemC is being used at a much higher," Domic said. "I do not see the conflict between SystemC and SystemVerilog."


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