Running start helps clear 90-nm hurdles

Back in 2004, fabless semiconductor maker Sandbridge Technologies Inc. couldn't get the performance it needed at the 0.13-micron IC process node. The wireless-telecom provider took a risk and became one of the first companies to try the relatively untested 90-nanometer node.

"We felt out on a limb, because not many companies were doing it," said Gary Nacer, vice president of engineering at Sandbridge (White Plains, N.Y.). On paper, Nacer said, 90 nm looked great. But in the real world there were problems, such as leakage current, on-chip variation and signal integrity.

Because 90 nm was new technology, Sandbridge designers were unsure how well-characterized the models were. They put a heavy focus on timing analysis, spent a lot of time grappling with signal integrity and built in sufficient margins to cover the potential impact of process variations, Nacer said. The result was a successful tapeout at the end of 2004.

Two years later, 90-nm design is fast becoming mainstream. According to Gartner Dataquest, 19 percent of ASIC design starts were at 90 nm in 2005, and that number will grow to 32 percent in 2006. Design tool vendors Synopsys, Cadence Design Systems and Magma Design Automation all report that around one-third of their customers are currently working at 90 nm.

The good news is that there have been several hundred 90-nm tapeouts. Silicon intellectual property is available, EDA reference flows are in place and there are well-known techniques for managing power concerns. The bad news is that masks still cost around $1 million or more, design costs are higher, and you'll probably have to adopt a low-power methodology and pay more attention to signal integrity, variability and manufacturability.

Design at 90 nm "is not rocket science," said Ravi Srinivasan, director of engineering methodology at fabless ASIC provider Open-Silicon. "But you need to be aware of the major design challenges, primarily from power, signal integrity, design-for-test and manufacturability. Make a diligent effort up front in the design to take care of each aspect, rather than pushing them toward the end of the design."

"The most important thing to know is that 90 nm is not difficult," said Ed Wan, director of design services marketing for Taiwan Semiconductor Manufacturing Co. "But remember that 90 nm is the first node where power becomes a primary design criterion. You need to study up on low-power techniques--mainstream ones like multiple-threshold libraries and more sophisticated ones like voltage islands, dynamic voltage scaling and MT [multithreshold] CMOS."

"If you go to 90 nm, you're a couple of years into the process," Nacer observed. "The technology is proven, but you need to make sure your methodology is in place. Make sure your timing analysis is well-implemented, pay attention to how clocks get routed. And OCV [on-chip variation] is an issue you'll have to deal with."

Designers are moving to 90 nm because the smaller die size can reduce cost, boost capacity and allow more integration of functionality onto a single chip. These attributes are particularly important in the consumer market. Reducing power is another reason, and that was a key motivation for Integrated Device Technology Inc., a San Jose, Calif., provider of communications ICs.

Mark Bauman, director of design engineering at IDT, said his division's first 90-nm chips were for content-addressable memories (CAMs), which dissipate a lot of power. "Dropping to 1 volt gave us a huge savings," he said. "We had the headaches of leakage current, but 40 percent lower active power."

Graphics, communications and networking are the primary applications for 90-nm chips these days, said Walter Ng, senior director at Chartered Semiconductor Manufacturing Ltd. One thing they all have in common is enough volume to justify the higher mask costs. "Folks who drive the volume can amortize the higher NREs [nonrecurring engineering charges]," Ng said.