BeSang, Albany Nanotech devise 3D memory

BeSang (Portland, Ore.) on Thursday (April 6) also said that it has formed a joint research project with the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. As part of a three-year program, valued at $1.1 million, BeSang will use tools and facilities at CNSE’s Albany NanoTech complex to advance its 3D technology.

Little-known BeSang is developing 3D technology that allows a memory core to be stacked on top of the logic layer within a semiconductor device. The company's proprietary "floating memory" technology enables high speed semiconductor device operation with a high-density memory core, said Kenneth Lee, director of business development for BeSang.

While conventional 3D chip technologies are package-level stacking technologies, which are good for limited mobile applications, BeSang’s 3D technology stacks multi-layer devices within a single chip, using seamless and unlimited interconnections between the device layers, according to the company. As a result, this single-chip, high-density 3D technology provides a low-cost, high-speed vertical memory solution for the semiconductor industry.

The company is said to use a wafer-level or “metal bonding” technology to develop 3D products. In the first step, the company will combine separate logic and silicon-on-insulator (SOI) wafers. Then, it will use a flip-chip process, thereby enabling a 3D design.

“We don’t combine two chips together,” Lee said in an interview. “We use metal bonding to combine memory and logic devices.”

The company will enter the semiconductor memory business for both the stand-alone and embedded memory markets. It plans to license its technology via an intellectual-property (IP) business model.

BeSang was founded in 2003 by Sang-Yun Lee. A former executive at Samsung, IDT and Motorola, San-Yun Lee is the chief executive of the startup. The company has received bridge funding from an undisclosed source.