Tool claims first transistor-level closed loop PLL verification

SAN FRANCISCO — Claiming an industry first, EDA startup Xpedion Design Systems Inc. introduced a transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter.

According to Xpedion (Milpitas, Calif.), the breakthrough allows PLL designers to fully verify their designs prior to silicon to save design spins and reduce time to production.

Phase-locked loops are present in a majority of complex ICs produced today in many applications. They also represent one of the most challenging design hurdles to overcome, and are, according to Xpedion, often the reason for failing silicon. But, the company claims, its GoldenGate simulator has the capability to ensure preoper PLL operation. Xpedion said it developed the technology with close partners and validated its through measure silicon.

"We are able to address a clear need in the industry to verify proper PLL operation through our advanced capabilities," said George Estep, Xpedion's director of applications engineering, in a statement. "This capability will save our customers painful design iterations allowing them to get their products to market faster."

Pricing and availability information were not provided. Xpedion said it is engaging with existing customers on this technology through partnerships and service agreements.