TSMC speeds up 45-nm intro

SAN JOSE, Calif. — Seeking to take the lead in foundry technology, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) on Wednesday (May 17) disclosed some of the first details of its new and advanced 45-nm process, with plans to accelerate the introduction of the offering in 2007.

But at the same time, the silicon foundry giant appears to have hit a brick wall with certain elements of the 45-nm technology. The company will most likely push out the adoption of high-k gate dielectrics and metal gates from the 45-nm node to the 32-nm node, according to an executive from TSMC (Hsinchu, Taiwan).

Initially, the company plans to release a low-power version of its 45-nm process, followed by other variations of the technology. Originally, TSMC planned to move into “risk production” for the low-power, 45-nm technology in the fourth quarter of 2007.

Now, the company has pulled in its introduction date and plans to move into “risk production” in the third quarter of 2007, said Shang-Yi Chiang, senior vice president of research and development, during a presentation at the company’s technology forum here.

TSMC’s 45-nm process is a 10-metal-layer technology, with gate lengths said to be down to 26-nm, according to Chiang. The process itself is equipped with copper interconnects, strained silicon, triple-gate oxide and a second-generation low-k dielectric film.

As expected, TSMC is expected to insert 193-nm immersion lithography tools for production at 45-nm, Chiang said. The company is reportedly using 193-nm immersion scanners from ASML Holding NV of the Netherlands.

At 45-nm, the silicon foundry giant plans to deploy a low-k film with a “k factor” of 2.5-to-2.6, Chiang said. The company is using low-k films with a rating of 2.9-to-3.0 for its 90- to 65-nm processes — based on Applied Materials Inc.’s Black Diamond-enabled chemical vapor deposition (CVD) technology.

Like all leading-edge chip makers, TSMC is scrambling to deploy high-k and metal gates at the 45-nm node. But the chances that TSMC will deploy these technologies at 45-nm are “pretty low,” he said.

"We are still working on it," he said, saying TSMC has not ruled out the use of high-k or metal gates at 45-nm. Instead, the company will most likely continue to extend silicon dioxide or a variation of the technology at 45-nm, pushing out high-k and metal gates at the 32-nm node, he added.