TSMC speeds 45-nm process launch

San Jose, Calif. -- Bidding to get a jump on its rivals, Taiwan Semiconductor Manufacturing Co. Ltd. last week disclosed the first details of its new 45-nanometer process, saying it plans to accelerate the introduction of the technology in 2007.

The approach's 10-metal-layer technology permits gate lengths down to 26 nm, according to the company. The silicon foundry giant also said that the 45-nm process is equipped with copper interconnects, strained silicon, triple-gate oxide options and a second-generation low-k dielectric film.

As expected, TSMC will make use of 193-nm immersion lithography at the 45-nm node. But, like most leading-edge chip makers, TSMC (Hsinchu, Taiwan) appears to have hit a stumbling block with certain elements of the technology. The company is working on advanced metal gates and high-k dielectrics for the gate stacks for its 45-nm process, but it may end up pushing out those technologies to the 32-nm node.

TSMC plans to start by releasing a low-power version of its 45-nm process, followed by separate general-purpose and high-speed derivatives. Originally, the company had planned to move into "risk production" for its low-power 45-nm technology in next year's fourth quarter. Now, it has pulled in its introduction date and intends to move into risk production in the third quarter of 2007, said Shang-Yi Chiang, senior vice president of research and development at TSMC.

"We are accelerating our 45-nm technology for release," Chiang said.

The world's largest foundry is announcing the aggressive process amid a new and strong growth cycle in the industry. The overall foundry industry declined by 2.2 percent in 2005, but the business is expected to rebound and grow by 19.8 percent this year, according to a new forecast from Gartner Inc. In 2007, Gartner expects the foundry market to grow a further 18.2 percent.

In the 45-nm era, TSMC hopes to reassert itself as a leader in the IC industry. Besides taking the early lead in the fledgling 45-nm foundry space, TSMC hopes to be on a par once again with the leading-edge IDMs.

In January, Intel Corp. (Santa Clara, Calif.) disclosed the initial details of its 45-nm process and claimed it had produced the world's first chips based on the technology. Intel said that it will be in mass production during the second half of 2007.

TI plans to sample devices based on its yet-to-be-announced 45-nm process in 2007, with production due in 2008, said Peter Rickert, platform manager for application-specific products at TI.

However, given the technical hurdles foreseen at the 45-nm node, only a few silicon foundries will have the expertise and resources to develop the technology, said Robert Lineback, an analyst with IC Insights Inc. Chip makers will contend with some new challenges and technologies, such as immersion lithography, high-k dielectrics, metal gates and ultralow-k, Lineback pointed out. "The question is: Can the foundries do it? And do their customers even want that technology?" he asked.

Perhaps the most radical chip-manufacturing step in TSMC's 45-nm process is the shift toward newfangled 193-nm immersion lithography scanners. At the 130-, 90- and 65-nm nodes, TSMC used conventional 193-nm "dry" scanners to process the critical layers in a chip design.

The first immersion scanners in the market, however, introduced some troubling problems--such as microbubbles and water residue on the wafer--that caused a new and alarming set of defects. Chiang said that TSMC has solved many of the problems with immersion, bringing the defect level down to the "single digits."

Low-k, high-k
For interconnects, TSMC is taking a less radical approach, especially with low-k dielectrics. At 45 nm, the foundry plans to deploy a chemical vapor deposition (CVD)-based, low-k film with a "k" factor of 2.5 to 2.6, Chiang said.

The company is already using low-k films with a k-factor of 2.9 to 3.0 for its 90- to 65-nm processes. In these processes, TSMC is using Applied Materials Inc.'s Black Diamond-enabled CVD technology. Chiang would not say if TSMC would use Black Diamond at the 45-nm node.

As it did for its 90- and 65-nm pro- cesses, TSMC will offer a triple gate oxide option that facilitates three oxide thicknesses on a single chip. The triple gate oxide removes design restrictions caused by various core-and-I/O combination requirements.

And, like all leading-edge chip makers, TSMC is struggling with the deployment of metal gates and high-k ma- terials for gate stacks at the 45-nm node. "We are working on [high-k and metal gates]," TSMC's Chiang said, but "the chances that TSMC will deploy these technologies at 45 nm are pretty low. That's my opinion." Instead, the company will likely continue to extend silicon dioxide, or some variation, at the 45 nm node, he added.