NEC tips 55-nm process with high-k, immersion

SAN JOSE, Calif. — NEC Electronics Inc. has rolled out what the company claims is the industry's first 55-nm standard CMOS process technology for use in next-generation, system-on-a-chip (SoC) designs with ultra-low power consumption.

A shrink version of NEC Electronics' 65-nm technology, the UX7LS process features the company's UltimateLowPower technology. This reduces power consumption in standby mode to approximately one-tenth of conventional 65-nm devices, and also boosts the transistor's on-current by 20-to-30 percent, according to NEC (Tokyo).

NEC's process claims to use 193-nm immersion lithography and a hafnium-silicate film as a high-dielectric-constant insulator film. UX7LS inherited the "on-grid design-ruled design for manufacturing (DFM) scheme" from the previous 65-nm generation.

The technology can reduce SRAM size to 0.446-square-micrometers, said Kazu Yamada, vice president of custom SoC solutions strategic business unit at NEC Electronics America (Santa Clara, Calif.).

"With our new process technology, SoC designers will be able to reduce power consumption and costs through device miniaturization compared to conventional 65-nm transistors," he said in a statement.

Shipping of engineering samples based on the UX7LS technology is expected to begin in the summer of 2007, and mass production is expected in the same year.