As the Design Automation Conference opens this week in San Francisco, North American chip designers seem to be happier with EDA tools and vendors than they were one year ago. But as the "EE Times 2006 EDA Users Survey" shows, IC designers still have deep concerns about, and various problems with, nanometer chip designs.

The research, conducted online between May 10 and May 22, in fact comprises three distinct surveys, on the design of chips, field-programmable gate arrays and pc boards. EE Times readers and TechOnline subscribers in North America, Europe and Asia were solicited by e-mail and asked to complete one of those three modules (see box, page 30).

Some commonality was found across the three surveys and geographies. In general, design tool users are most satisfied with EDA technology and accuracy, and least satisfied with pricing,

licensing and interoperability. North American-based engineers who participated in the IC and FPGA surveys generally expressed more overall satisfaction than engineers in the 2005 surveys, which focused on North America.

The 2006 IC survey shows a move to finer process geometries, with 65-nm chips now in progress worldwide. Engineers in all geographies foresee increases in gate counts and clock speeds within two years.

Chip designers today are most concerned about functional verification and timing closure. But as feature sizes shrink, they expect that managing leakage current will become their biggest concern--even bigger than design-for- manu factur- ability (DFM).

Most Europeans and Asians acknowledged that their latest IC design project ran late, while in North America, nearly half of the most-recent projects were late. North American designers cited a mean cost of $15 million per chip design project. EDA tool budgets are relatively stagnant in North America but are rising in Asia.

One surprising finding is that only a minority of companies are outsourcing portions of chip design. And when they do outsource, they most frequently use companies in their own geographic region, although there's a growing trend for North American companies to go overseas.

Vendor usage and satisfaction ratings indicate that Cadence Design Systems Inc. has gained some ground in North America. Indeed, a geographical pattern can be discerned in respondents' vendor ratings: For many of the criteria, North American engineers most often favored Cadence, Europeans chose Mentor Graphics Corp. and Asians stuck with Synopsys Inc.

Geometry down, complexity up
The IC design survey included responses from 215 North Americans, 43 Europeans and 109 Asians, along with a few respondents who didn't indicate nationality. About half the Asians hailed from India, and most of the rest were from China or Taiwan. Most respondents described themselves as design engineers rather than managers, and companies of all sizes were represented.

In North America, 56 percent of current chip designs still use 0.13-micron or larger line widths, and 26 percent are at 90 nm. But 16 percent are at 65 nm, compared with just 5 percent in last year's survey, and 2 percent are already working at 45 nm.

In two years, 45 percent of North American designers expect to be working at 65 nm and below; of those, 18 percent expect to be working at 45 nm. European and Asian engineers are just slightly behind in their use of 65-nm technologies today, and their expectations two years out are less aggressive by a few percentage points.

Gate counts are high and rapidly rising. In North America, the mean total equivalent gate count is 14.1 million, with 21.9 million expected in two years. Mean figures for Europe are 10.6 million gates today and 15 million in two years; for Asia, the mean is 6.1 million today and a projected 15.7 million in 2008.

Asia-based respondents expect to move faster in clock speeds. Two years out, they expect a mean clock speed of just over 1 GHz, excluding I/Os. North American designers expect a mean clock speed of 933 MHz in that time frame. North American designers cited the survey's fastest current mean clock speed, at 749.5 MHz.

Many IC designs run over schedule. Forty-six percent of respondents in North America, 56 percent in Europe and 57 percent in Asia said their most recent chip project was late. Engineers in all regions said the biggest contributors to delays are changes in requirements or specs. Of respondents who said their latest project was late, 64 percent in North America said the projects had needed a silicon respin, as did 46 percent in Europe and 50 percent in Asia.

Respins boost the cost of chip design projects. The IC survey asked those responsible for setting EDA budgets about the total cost of their latest IC design project. Among the 41 North American respondents to the question, the mean cost was a whopping $15 million. Mean European and Asian costs were around $3 million, but the sample sizes were small.

Fifty-nine percent of the North Americans said their 2006 EDA budget is the same as in 2005, while 33 percent said the 2006 budget is "more" or "much more" (see By the Numbers, page 32). Among Asia-based engineers, however, 71 percent said their 2006 EDA tools budget is "more" or "much more." Further, 85 percent of engineers in Asia said they're experiencing more design starts in 2006 than in 2005, compared with 61 percent of those in North America.

Outsource surprise
Given the growing complexity and increasing costs of design, one might expect that most companies would do some outsourcing to third parties. That's not the case, although a hefty 38 percent of North Americans, 47 percent of Europeans and 44 percent of Asians said their companies outsource a portion of chip design activities.

Which functions are being outsourced? In North America, 15 percent said their companies turn over IC physical verification to a third party, 14 percent cited IC layout and 12 percent cited DFM. Europeans outsource more--28 percent, 23 percent and 19 percent in these categories, respectively. Asians outsource the least, with 7 percent, 9 percent and 12 percent in the three respective categories.

When those who said their companies outsource were asked where their outsourcing partners are located, most cited their own geographies (see page 32). For example, 68 percent of respondents in North America said their companies outsource to North American firms. It's worth noting, however, that this figure is down from 90 percent in last year's survey.

Further, 34 percent of the North America-based respondents to the outsourcing questions said their companies outsource to India, compared with 24 percent in last year's survey, and 16 percent cited China/Taiwan, a slight decrease. (Totals exceed 100 percent because respondents were asked to check all that apply.)

We also asked about the types of third parties used for outsourcing. In all geographies, independent design consultancies are the first choice.

Leakage looms
One purpose of the EDA users survey is to discern the technical challenges designers face now and those they expect to face in the future. In North America, 63 percent of designers said completing functional verification is "very critical" at current process nodes, making it the top concern. Other key challenges at present process nodes are meeting timing budgets and meeting dynamic-power budgets.

What will get worse as process nodes shrink? A common answer was meeting budgets for leakage power, cited as critical today by 42 percent of the North America-based respondents and as a looming concern by 60 percent. DFM, in comparison, is viewed as critical by 36 percent of those designers today--low on the list of concerns--though 44 percent expect it to get worse (see page 32).

Respondents in Europe and Asia also pointed to leakage as the most significant emerging concern: 51 percent of those in Europe and 38 percent in Asia called leakage "very critical" at current nodes. Asia-based designers are more concerned about leakage than dynamic power, even today.

The survey revealed some geographical trends around EDA tool usage. In all geographies, tools for formal verification, design-for-test and physical synthesis are widely used; C-language synthesis tools, analog synthesis and resolution enhancement technology are not.

SystemVerilog finds its strongest support in Asia, where 41 percent use the language today and 38 percent plan to use it within two years. North America is close behind--36 percent today, 34 percent in two years. Europe, by contrast, is strongest in SystemC: 35 percent of respondents are using that language today and 24 percent plan to adopt it within two years.

Moreover, about 30 percent of North Americans and 40 percent of Europeans and Asians expect to be using C-language synthesis in two years.

Users also evaluated EDA tools across a variety of criteria. Designers in North America are most satisfied with EDA vendor support, and with tools' accuracy and ability to handle large designs. They are least satisfied with multivendor interoperability, cost of purchase and cost of ownership. All categories except for ease of use scored higher on the satisfaction scale year than last.

Established tools such as synthesis, placement and physical verification fared best on the satisfaction scale; newer tools like system-level design, signal integrity analysis and power analysis scored lower.

Thirty-seven percent of North Americans, 30 percent of Europeans and 36 percent of Asians said they use internally developed tools (not counting scripts). Common internal tools include architectural definition, system-level modeling and analog/mixed-signal design.

There's also a place for startups. Twenty-two percent of North Americans, 14 percent of Europeans and 23 percent of Asians say they've purchased from EDA startups. And 56 percent of North Americans, 33 percent of Europeans and 68 percent of Asians say they have been "very" or "somewhat" satisfied with the outcome.

We asked users to evaluate vendors in general. Users are "very" or "somewhat" satisfied with technology, ease of use and support. They are least satisfied with licensing and pricing. Asians seem to be more satisfied in every category than Europeans or North Americans. But North Americans expressed higher satisfaction with all listed criteria--technology, ease of use, support, quality of software, training, inter- operability, sales reps and pricing--this year than in 2005. The biggest gains were in training, interoperability and pricing.

Predictably, the three most-used EDA vendors are the three largest: Synopsys, Cadence and Mentor. But No. 4 may be a surprise: The Mathworks, provider of Matlab. Next, in order, come Synplicity, Novas, Magma, Denali, Agilent EEsof and Tanner.

In the surveyed regions, Synopsys (93 percent of respondents) and Mentor Graphics (84 percent) are most widely used in Europe, and Cadence is most widely used in North America (81 percent). In North America, differences in usage between 2005 and 2006 were generally small. But when asked to identify a primary EDA vendor, 44 percent chose Cadence in 2006, up from 37 percent in 2005. Thirty-two percent chose Synopsys in 2006, down from 40 percent in 2005.

As in previous years, Novas Design topped the user satisfaction ratings: 83 percent in North America, 100 percent in Europe and 69 percent in Asia are "very" or "somewhat" satisfied. The big three vendors are almost equal in North America--66 percent are "very" or "somewhat" satisfied with Synopsys, 65 percent with Cadence, 63 percent with Mentor. But Asians like Synopsys best (80 percent) while Europeans are happiest with Cadence (66 percent).

We asked respondents to rate vendors across 15 attributes, such as after-sales support, competitive prices, support of open standards, technology leader today, technology leader in three years, training and knowledgeable sales reps. North Americans most often chose Cadence, Europeans most often chose Mentor and Asians named Synopsys in almost every category. One exception: all three said that Cadence, initiator of the OpenAccess project, had the best integration with other vendors' tools. n

-- Editor's note: The FPGA and pc-board surveys will be described in subsequent issues.

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Electronic Design Automation Branding Study

Respondents offer industry wish list

Respondents to the "EE Times 2006 EDA Users Survey" had a chance to state the one message they'd most like to pass along to EDA vendors. Here are a few of their responses:

" Support open standards and make the tools interoperable among vendors."

" A customer who buys an expensive EDA package should be given a guarantee that there will not be excessive price increases for support."

"After integrating many tools from acquired vendors, the user interface needs to be rewritten from the ground up to improve design productivity. You should always be thinking of how to reduce the number of operations, particularly on common tasks."

"Better after-sale support."

"Don't shortchange support and development for those of us not out on the bleeding edge. Mixed-signal design still has a lot of opportunity at 0.18 to 0.50 micron."

"Fix the bugs."

"Get pricing in line with reality."

"I want perpetual licenses."

"If a company owns two tools, then I expect the handoff between the tools to be seamless. I have yet to see this basic business practice."

"Integration of back-end and front-end tools is very important. Clock tree synthesis is critical in [the] back end, and current tools do not do a good job."

"Please improve timing analysis."

"Please make tools as bug-free as possible. We can't afford to spend time debugging tools. Stress the tool to a maximum extent, and then release it for production."

"Please work out a better pricing mechanism while dealing with customers in Asia, where cost is a bigger concern. Remember it just takes a few million dollars to start up in these places, while the American and European startups start with a capital of at least $100M."

" Stop the hype and apply the marketing dollar savings to R&D. And ease up on the DAC spending."

"Usability is awful. It seems that the user interfaces are written by professional software hacks and that real IC designers have no input. You would do well to get usability feedback from experienced designers."

" I am generally quite satisfied with the current state of EDA. The front-end tools are better, but the back end needs more work (because it is harder). Keep up the good work. My job is a lot easier because of your work."