NAND test costs soar out of control

NAND test costs soar out of control
SAN JOSE, Calif. — The NAND flash-memory market is exploding, but there's trouble looming in the sector: test costs are soaring out of control and escalating by up to 70 percent per chip density.

In recent times, suppliers of automatic test equipment (ATE) have announced new, high-speed NAND flash testers, which are equipped with the latest and greatest test handlers. The new gear is supposed to keep up with the explosion in NAND densities and volumes by using conventional parallelism techniques. Advantest, Nextest and Verigy are the main NAND flash-memory ATE suppliers in the market.

But, while ATE vendors are somewhat getting a handle on logic and system-on-a-chip (SoC) test costs, ATE suppliers — the chip makers themselves — are behind the curve in NAND flash.

"The ASPs for NAND have fallen by 50 percent since the beginning of the year," said Tim Moriarty, vice president of sales and marketing for San Jose-based Nextest Inc., a high-flying supplier of ATE. "Unfortunately, the test times are getting longer."

For today's leading-edge devices, it can take a whopping 10-to-30 minutes in order to test each NAND flash-memory part, said Jim Mulady, editor of The Final Test Report, a newsletter that covers the ATE industry.

"In the future, we're looking at 60 minutes each," he warned. "Logic is going the other way. BIST and other technologies are driving the cost of logic test down."

In contrast, NAND flash lacks a viable built-in-self-test (BIST) or scan solution, causing headaches for suppliers of these parts, namely Hynix, Intel-Micron, Toshiba and Samsung.

"In addition to standard protocols, most flash manufacturers use proprietary signaling interfaces and test methods," wrote Gary Fleeman, product manager for ATE giant Advantest America Inc. (Santa Clara, Calif.), in the recent issue of EE Evaluation Engineering. Advantest America is the U.S. sales arm of Japan's Advantest Corp. (Tokyo).

Some chip makers hope to address at least one problem in the arena. Seeking to accelerate the time-to-market for NAND-based flash memories in the marketplace, Hynix, Intel, Micron, Phison and Sony recently formed a new and long-awaited working group in the arena. The organization, dubbed the Open NAND Flash Interface (ONFI) Working Group, are defining an enhanced chip-level standard interface for the attachment of NAND flash memory to host systems, ostensibly to reduce product cycle times.

Still, the overall problems persist in NAND test costs. "Special test challenges result when testing flash memory devices," according to Nextest in a recent S-1 filing with the U.S. Securities and Exchange Commission (SEC). Nextest made the filing, when it recently announced its initial public offering (IPO).

"Each memory byte within a flash device tests at a different rate. This is fundamentally different than testing DRAM devices where each DRAM byte takes the same amount of time to test. In high volume manufacturing, multiple flash memory devices are simultaneously tested by a single tester, in what is called parallel test," according to Nextest.

"If ATE systems are required to wait for testing of the slowest byte to be completed before moving on to testing the next set of bytes, the overall test time can dramatically increase," according to the firm. "This problem is compounded by the increasing density of flash memory devices as well as the larger number of flash memories being tested in parallel. In order for the testing of ICs not to become prohibitively expensive, flash memory manufacturers require ATE that is optimized for the special testing needs of flash memory."