Designers give CAD research gurus an earful

Phillip Restle, research staff member at IBM Corp.'s T.J. Watson Research Center, outlined tool needs for clock-distribution design. These include shielded length-matched routing, frequency-dependent transmission-line models, statistical timing and simulation-based tuning using complex objective functions. "This is a unique problem that needs unique tools," he said.

ESL and verification
Any doubts about the reality of electronic system-level (ESL) design may have been erased by a presentation from Pascal Urard, high-level synthesis manager at STMicroelectronics. That company's SystemC-based high-level synthesis flow, he said, has improved design productivity with a fast, compact high-level model for both synthesis and simulation. It also allows a rapid exploration of many architectures.

But tool enhancements are needed, he said. Gate capacity is still low, there's no assertion-based verification in C-language models, multiple clock designs aren't supported and most ESL tools focus on data path rather than control logic. Urard hopes to see "design space exploration" tools that allow exploration at a very high level and would transform C/C++ into synthesizable SystemC.

"We need academia and the EDA community to think at the flow level, not only at the tool level," Urard said.

Traditional spreadsheet-based analysis is not good enough for system-on-chip architectural design, said Tor Jeremiassen. A member of the technical staff at Texas Instruments Inc., he called for tools that can model traffic scenarios, intellectual-property interaction and system functionality. The goal, he said, is a performance analysis that will allow informed trade-offs to optimize power, performance, area and schedule.

When it comes to verification, "speed is everything," said Tse-Yu Yeh, director of architecture and verification at PA Semi. He described a simulation and emulation environment in use at his company that includes emulators from Eve SA, synthesis from Synplicity and debugging from Novas Software. Challenges, he said, include gated clocks, potential mismatches between simulation and emulation, and a lack of coverage for FPGA-based emulation.

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