Embedded superlattice slashes gate leakage

Others have opted to use silicon- on-insulator (SOI), which achieves lower parasitic capacitance and re- duced junction leakage by virtue of an embedded oxide layer that effectively isolates transistors from each other. But like strained silicon, SOI has limitations below 65 nm. And neither strained silicon nor SOI directly addresses the problem of gate leakage.

Mears Technologies' technique involves inserting "epitaxially grown silicon into a standard CMOS flow as a channel replacement layer. The net result of is two-dimensional, sheet-like behavior, compared with standard, 3-D epitaxial silicon," said Mears.

Called silicon-on-silicon, the structure is basically a superlattice laminate, about 100 angstroms thick, in which the silicon atoms are spaced out slightly more in the vertical direction than in the plane of the device, thereby creating channels for electrons and holes to travel parallel to the surface more easily, while blocking vertical conduction between the gate and the channel.

"In the plane of the device, the electron density is more distributed or delocalized, thereby achieving a lower effective mass or a higher mobility in that plane," Mears said. "But in the vertical direction, this material is anisotropic [using an etch rate in the direction parallel to the surface that is lower than the etch rate used in the direction perpendicular to the surface], giving it a higher effective mass and lower conductivity in the vertical direction. That gives our technology its inherent gate leakage reduction capability."

"They are putting down mono- layers, some of which are highly conductive, and they alternate with layers that act to prevent the gate leakage that occurs in the vertical direction," said IC Insights' Yancey.

The superlattice merely adds a few processing steps to the process for making normal transistor channels. Adopters thus can easily insert the extra steps without upsetting their current processes or their plans for extending those processes down to 22 nm, according to the company.

"The industry is crafting many technologies to get to 45 nanometers, and all of those can be fit to our platform," said Neil Vasant, CEO designate at Mears Technologies. "For those who already have strained silicon or SOI, our technology brings yet another layer of benefit and investment return by squeezing out yet more performance or further lowering power consumption."

Since no new materials need be introduced to use Mears Technologies' channel replacement technology, it can be added to fabrication facilities with a minimum of fuss. For its tests, Mears Technologies used standard development and production tooling on an ASM Epsilon 2000. That single-wafer epitaxial reactor series is readily available, with more than 500 units said to be operating in the field.