Soaring data rates signal coming crisis

SANTA CLARA, Calif. — Engineers want a new bag of tricks to manage signal integrity as data rates soar into multigigahertz territory. Meanwhile, researchers disclosed fresh work at last week's DesignCon here that will push next-generation systems past 20 Gbits/second.

As today's systems press toward 6-Gbit/s serial interconnects, they face so much signal loss and distortion that they can no longer be designed or tested using conventional methods. Power and interference issues are creating other potholes.

The problems will only get worse. Engineers are beginning to implement PCI Express 2.0, which operates at 5 GHz, and they are discussing a 3.0 standard that could hit 8, 10 or 12 GHz. The Fibre Channel community is already working on an 8-Gbit/s version, and the IEEE is studying a next generation of Ethernet that could hit 100 Gbits/s.

"Three things that were once independent issues are coming together—signal integrity, power integrity and electromagnetic compatibility," said Istvan Novak, a signal integrity staff engineer from Sun Microsystems Inc. who chaired two panels at DesignCon. "Now it's all one big mess that we have to sort out, and most of the time we don't have sufficient data."

"A couple of years ago, we saw serdes [serial transceiver chips] coming on and thought they would be easy to design," said Ian Dodd, an architect for high-speed tools in the board division of Mentor Graphics Corp. "Now we see problems with the weave of materials in the board. Meanwhile, people are pushing serdes to their limits, creating more problems with the materials and power supplies."

Mentor is doing internal demos of a tool that would take power and board material effects into account as part of signal integrity design, Dodd added.

Smoothing out the boards

In this environment, chip and board makers are calling for a standard approach to signal integrity. The standard would replace separate, sometimes conflicting signal integrity test procedures written into the specifications for interconnects such as PCI Express, Fibre Channel, Infiniband and fully buffered DIMMs.

"Right now, it's not only handled differently for each standard, but every company in each standards group has its own approach," said Bryan Casper, who manages a signal research lab in the corporate technology group at Intel Corp.

A groundswell is building for an ad hoc group to establish a standard that could later be taken to a formal standards body, said Terry Morris, a fellow in Hewlett-Packard Co.'s server group. "The IPC will need to be involved in this, but we need a solution sooner" than the pc-board group could deliver one, Morris said.

The standard will likely be implemented in vector network analyzers and involve highly skilled probe techniques, he added. Driving the need are problems with signal loss cropping up in mainstream boards, many of them made in China, Morris said.

"When it's in a high-end system, you can come up with your own solution and add some costs," he said. "But now we see this across many interfaces and in low-end systems."

"Everywhere I go, there seems to be a different methodology in high-speed design," said Robert Haller, a hardware architect at Enterasys Networks who chaired a panel on best practices in high-speed serial design.

Interrogating the chips

A separate effort hopes to define a standard way to test high-speed transceivers. The chips use a variety of often proprietary equalization techniques to send fast serial signals across a board, even when distortion keeps conventional oscilloscopes from verifying the signal exists.

"By the time the signal gets to the receiver, there's nothing we can measure for compliance. We have nothing to validate against," said Todd Westerhoff, vice president of software products at Signal Integrity Software Inc. (Maynard, Mass.). At DesignCon, SiSoft showed its Quantum Channel Designer, a tool for designing serial interconnects with data rates of 5 Gbits/s and beyond.

Today chip makers create their own transceiver models, often using homegrown software. That prevents OEMs from modeling high-speed interconnects using chips from multiple vendors.