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Zenasis folds, sells assets to Open-Silicon

Richard Goering

5/4/2007 5:17 PM EDT

Zenasis Technology, a provider of transistor-level optimization tools for IC design, has sold its intellectual property (IP) assets to fabless ASIC provider Open-Silicon Inc. and has apparently shut its doors. Open-Silicon will use Zenasis' technology to try to bridge the gap between custom and ASIC design, said Naveed Sherwani, Open-Silicon president and CEO.

"We were at a position where the decision was made by our investors and management that it would be good to pursue some other course for the company, and through that course we ended up here," said Vamsi Boppana, former vice president of engineering at Zenasis and now engineering director at Open-Silicon. Boppana said Zenasis management is "wrapping up operations." As of Friday, May 4, the Zenasis web site was still on line, but the company's main phone number had been disconnected.

Zenasis was founded in 2000, and it quietly released its first product, the ZenTime cell-based timing optimization tool, in May 2003. In November 2004, the company raised $7 million in third-round venture funding, bringing the total invested in the company to $17 million. Subsequent investments raised that total to over $20 million, Boppana said.

Zenasis products included ZenTime-GT, a gate-level timing optimization tool; ZenTime-XT, a transistor-level timing optimization tool; ZenTime-CT, an automated cell generation flow; ZenTime-AT, an area optimization tool; and ZenTime-PT, a leakage power optimization application that facilities the use of low voltage threshold cells in multiple-threshold designs. Customers included Agilent Technologies, Panasonic, Raza Microelectronics, Texas Instruments, Micronas, Renesas, and Samsung.

Boppana said Zenasis had 12 employees, and 6 have joined Open-Silicon. "We felt the technology would find a better home in a model where we could work much more closely with customers in a turnkey environment and where we are not dependent on flows," he said. "It's not so much that we couldn't have carried forward for a while and made incremental progress, but we felt this was an opportunity that could give a quantum leap to the technology."

Zenasis' technology doesn't really belong in an EDA model, said Sherwani. "The technology is clearly sophisticated and has a long history of academic research," he said. "But what the technology does not have is ease of use. The point is, this is not something an average engineer could use right away, which is a critical need for a standard EDA tool."

But the technology is valuable, Sherwani said. "I've been a fan of this technology since I was a professor. I've written papers on this subject myself," he said. "But I always felt that making an EDA tool out of that would be challenging."

In a letter posted last year at the Deepchip web site, Zenasis CEO Dennis Harmon alluded to this challenge. "When I first got to Zenasis, our tools were focused on 'power' users who had their own fabs," Harmon wrote. "Our tools were too complex and hard to deploy for fabless designers. Since then I've pushed the company to make a new set of tools which are simpler and more self-contained."

The Zenasis technology is extremely valuable to Open-Silicon, Sherwani said. "One outstanding problem in the ASIC industry is that we do not have the speed from microprocessor cores to build the next generation ASIC," he said. "One obvious application is to use this technology to get that speed."

Sherwani also noted that Zenasis technology can "capture" custom IC design technology into design tools. "With the help of the team we have here, we will be able to implement that technology into ASICs and make ASIC performance and power closer to custom-built chips," he said.

Open-Silicon will not sell the Zenasis tools externally, Sherwani said, because the company is not an EDA vendor. "Our intention is to support current [Zenasis] customers so they are not disrupted, yet not defocus ourselves," he said.

Open-Silicon is a fabless ASIC company that claims to provide a low-cost, low-risk alternative to traditional ASIC design and development. The company recently announced a multi-layer mask program to help drive down mask costs.





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