X86 war cuts to the cores

The Larabee high-end visualization chip includes an array of X86 cores sharing a single cache and using a familiar X86 programming model. "Larabee is more like an experiment or a calculated risk in a new area for Intel," McCarron said, in a comment that might well have applied to all of the new SoCs.

The Tolapai device houses an X86 core along with a security accelerator, memory controller and various I/O interfaces. It aims to power a rising tide of networking appliances used in small- and midsized-business networks.

New interconnect
Intel announced plans at IDF to put an improved interconnect, called QuickPath, in its computer CPUs starting with the Nehalem family debuting in the fall of 2008, but it provided few details on the new link.

David Kanter, editor of the Real World Technologies Web site, compiled an ex- tensive analysis of QuickPath based on his reading of Intel patents on the technology. He concluded it runs at 4.8 to 6.4 GHz and offers links up to 20 bits wide.

By contrast, AMD's HyperTransport 3.0 is a 32-bit-wide bus, but its maximum speed is only 5.2 GHz. What's more, it won't appear on all AMD chips until sometime in 2009.

"AMD could be in serious trouble for six to 12 months," depending on the exact timing of bus upgrades and chip rollouts, Kanter said.

"We think Intel will have a performance advantage with QuickPath," said Richard Doherty, principal of market watcher Envisioneering Group (Sea- ford, NY). "I don't think they have all their figures of merit ready, but it looks good, and I don't think AMD can match it. It seems a better balance in bandwidth and latency than the AMD approach."

Intel and AMD are also competing in to convince third parties with cards and co-processors to hop on their separate I/O buses.

AMD is licensing a cache-coherent version of HyperTransport to such companies. Intel is licensing QuickPath to select companies, but it is recommending that most customers use Geneseo, its proposal for a version 3.0 of PCI Express that has some of the features but not all the complexity of a coherent bus and thus is easier and cheaper to implement.

"Ninety-five percent of the apps benefit from being on a bus like this," said Ajay Bhatt, chief I/O architect at Intel. The PCI Special Interest Group is rallying around the Geneseo proposal as a likely candidate for its Express 3.0 standard, Bhatt added.

Intel wants the Express standard to be adopted broadly because it helps simplify much of its software design. Even silicon blocks on Intel chip sets and processors often use PCI software semantics, although they ride a wider and faster, proprietary on-die interconnect, Bhatt said.

Eric Lemoine, chief architect of Tarari (San Diego), an accelerator company working with Intel, agreed that the Ex- press and Geneseo approach is the simplest for linking his chips with X86 hosts. He added, however, that the HyperTransport bus represents a better architecture.

"With HyperTransport, you can ac- cess and work at the level of the cache lines, and it offers low latency," he said.

Geneseo is a decent approach, but Lemoine said an even simpler way forward could come from making some adjustments to existing memory and I/O controllers. Today's Express parts typically don't return full 512-byte requests and don't relay data in sequential order--details that significantly slow the workings of a high-performance accelerator, he added.

Process edge
Some Wall Street analysts said AMD is under a serious long-term threat from Intel's process technology advantage. The process lead will help Intel maintain an edge in frequencies, cost and power, they said. Thus, AMD may gain market share and see rising average selling prices over the next year, but beyond that it will be hard for the company to maintain its position.

At IDF, Intel showed working versions of server, desktop and notebook processors using its 45-nm technology. The company said it would release about a dozen of the Penryn family CPUs on Nov. 12 and more in 2008.

Intel's high-k dielectric is a key part of that process. "Others have announced 45 nm, but none have hafnium-based dielectrics. We will be unique in this technology in the industry," said Otellini.

The Intel chief executive also showed a 32-nm test wafer comprised of working 291-Mbit SRAMs, each sporting 1.9 billion transistors. "This gives us the confidence to build mainstream micropro- cessors on this technology a short two years from today," he said.

Intel has set itself a demanding schedule of introducing a process technology every two years. It's a pace that AMD, which just shipped its first 65-nm processors--six months later than promised--will find hard to match.

For its part, Intel expects it will ship more 45-nm than 65-nm parts by next fall. "We have sent qualification samples of 45-nm server and high-end desktop processors to customers for their final qualifications," said Smith.