PORTLAND, Ore. -- Reducing noise in advanced graphene transistors by 10 times can be achieved with a novel bilayer architecture, according to researchers at the T. J. Watson Research Center at IBM Corp. (Yorktown Heights, N.Y.). As transistor
dimensions are reduced below 32 nanometers, noise becomes a big problem for all devices in any material--a problem that follows Hooge's rule. But if ways can be found to sidestep Hooge's rule and reduce that noise, then the higher speeds of smaller devices can be combined with increases in signal-to-noise ratio. IBM now claims to have found the solution for graphene transistors.
"What we have found is one plus one is equal to more than two--in other words, if we use just one graphene layer then the noise fluctuations are well known from other materials we have studied before. That is, in general, as you make devices smaller, the noise inherently increases regardless of the material," said IBM researcher, Yu-Ming Lin. "But what we find unusual and new about graphene is that when we add a second layer the noise is dramatically reduced by a factor of 10."
Graphene--essentially single-wall carbon nanotubes flattened out into sheets--offers higher electron mobility than does silicon when fabricated in a honeycomb lattice of pure carbon atoms in atomically thin monolayers. By fashioning transistor channels out of graphene, IBM and others hope to anticipate the next generation of semiconductors that outperform today's complementary metal oxide semiconductors (CMOS) cast in silicon.
Graphene offers advantages over carbon nanotubes, since it can be fabricated using lithography techniques, rather than manufacturing nanotubes and then trying to place then on substrates. Unfortunately, when shrinking graphene transistor channels into nanoribbons narrower than 32 nanometers in width, their signal-to-noise levels become intolerably low. But by fashioning bilayers, IBM claims to have solved that noise problem.
"Graphene sheets naturally form into sheets, and they have a natural separation that is very, very small," said IBM researcher Phaedon Avouris. "We believe by using by-layer deposition techniques, we can solve the noise problems that we have been facing with graphene transistors."