IBM, GIT demo 3D die with microchannel cooling

BURLINGAME, Calif. -- IBM, Georgia Institute of Technology and Nanonexus presented a technology that involves 3D devices with integrated microchannel cooling.

In a paper, the companies claimed to have demonstrated a 3D silicon die with a density of 2500/cm² -- and integrated with microchannel heat sinks.

With the technology, a microchanneled cooled processor at 3-GHz can operate at 83 Watts in 47 degree Celsius conditions, according to the paper. In comparison, an air cooled processor at 3-GHz operates at 102 Watts in 88 degree Celsius conditions, according to the paper.

The technology involves a 3D stacking technique called through-hole vias (TSVs). The problem with TSVs is to remove the heat in 3D structures, especially in microprocessor designs, said Deepak Sekar, an engineer at SanDisk Corp., who presented the paper at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week.

''When two 100W/cm² microprocessors are stacked on top of each other, for example, the net power density becomes 200W/cm² and is beyond the heat removal limits of currently available air cooling technology,'' Sekar said in the paper.

The paper proposes the idea of fabricating TSVs on a wafer. First, a chip is fabricated. Second, the chip is etched to form the fluidic TSVs and microchannels. This is a two-step lithography process.

Third, the device is spin coated and polished with a sacrificial polymer material. Then, the polymer is spun-on, patterned and cured to form a cover for the TSVs and microchannels.

The microchannels are said to be 200-um tall and 150-um wide. The copper TSVs are 50-um in diameter. Silicon thickness is 400-um, while copper density is said to be 2500/cm², according to the paper.

"Cooling fluid can be delivered to the 3D stack either using tubes on the back side of the 3D stack or using fluidic channels on the substrate,'' he said. ''The fluid is then delivered to the microchannel heat sinks on the back side of each chip in the 3D stack using fluidic through silicon vias and fluidic pipes.''

A two-chip 3D stack is said to show a junction-to-ambient thermal resistance of 0.24 degrees Celsius per Watt, according to the paper.

Chip scaling is showing no signs of hitting the wall--yet. But one alternative path--3D technology based on TSVs--continues to generate steam.

TSV technology took center stage at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week. Georgia Institute of Technology, IBM, IMEC, Fraunhofer, Tohoku University, TSMC and others presented papers on TSV at IITC, although there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.