Albany NanoTech readies new 300-mm R&D fab

Albany NanoTech readies new 300-mm R&D fab
ALBANY, N.Y. -- Albany NanoTech will shortly open a new facility--a massive operation that will focus on 22-nm R&D technology, post-CMOS processes and clean technology.

The previously-announced facility, NanoFab 300 East, is slated to open in early 2009. The $150 million project includes a 100,000-square-foot building, which itself will house a new and advanced 300-mm R&D fab.

It also includes an additional 250,000-square-foot office and laboratory building. This part will house the new headquarters of International Sematech, which recently moved its main office from Austin, Texas to Albany, thanks in part to generous incentives by the state.

It will also house a ''test farm'' in clean technology. One of the proposed projects in the facility is also 22-nm R&D. Leading-edge chip makers are just rolling out their 45-nm designs, with 32- and 22-nm in R&D. 22-nm devices could hit the market by 2011 or so.

The 22-nm effort is said to be led by IBM Corp.'s ''fab club." IBM and its partners already conduct R&D at Albany NanoTech. IBM's other joint development partners include, Chartered Semiconductor Manufacturing Ltd., Freescale Inc., Infineon Technologies AG, NEC Electronics Corp., Samsung Electronics Co. Ltd., STMicroelectronics N.V. and Toshiba Corp.

This week, IBM claimed to make a big breakthrough in 22-nm. Amid probable delays with extreme ultraviolet (EUV) lithography, IBM plans to extend 193-nm immersion and move towards ''computational scaling'' technology for the 22-nm node and perhaps beyond.

Current optical lithography is expected to hit the wall at the 32-nm node. ''Computational scaling'' is said to overcome those limits and extend 193-nm immersion.

A key to ''computation scaling'' is a partnership between IBM and Mentor, which plans to devise a new resolution enhancement technique (RET) to enable 22-nm designs and perhaps beyond. This RET technology is known as source-mask optimization, which is said to optimize both mask layout and illumination simultaneously to maximize image contrast in a scanner.

IBM, Intel and others are also conducting R&D for the 16-nm node and beyond, but the question is how far can CMOS scale? Some say 16-nm. Others believe below 10-nm, possibly 6-nm.