45-nm SOC process
At IEDM, meanwhile, Intel will describe a new 45-nm process derivative for SOCs. The process is still in the lab, but it could propel a new and important business for the chip giant.
Last year, Intel created a new SOC enablement group. Intel has stated it has at least four SoCs in the works for systems outside its traditional PC markets. Tolapai is aimed at storage networks, Silverthorne at handhelds, Larabee at high-end visualization systems and Canmore at wired consumer devices.
On the process front, the 45-nm SOC technology makes use of a high-k/metal-gate scheme that has been ''optimized for low power products,'' he said.
Within the process, the PMOS/NMOS logic transistor drive currents are 0.68/1.04 mA/um, respectively, at 1.1-Volt and offstate leakage of 1 nA/um. High voltage I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OPT fuses are employed.
And not to be outdone, Intel will demonstrate for the first time a high-speed, low-power quantum well field effect transistor. The p-channel structure will be based on a 40-nm indium antimonide (InSb) material, which is said to achieve a cut-off frequency (fT) of 140-GHz at a supply voltage of 0.5 V.
Transistors made on III-V materials are being explored in research as a means to provide improved performance and low power capabilities beyond what silicon may be able to provide.