Top 15 technology challenges for 22-nm node
At the recent International Electron Devices Meeting (IEDM) in San Francisco, most of the leading-edge logic papers dealt with the 32-nm node. IBM Corp. presented one of the few 22-nm papers.
In fact, leading-edge chip makers are currently in 22-nm R&D. So what are the big challenges involved at the 22-nm node?
A team of expert analysts from Semiconductor Insights, Xu Chang, Vu Ho, Ramesh Kuchibhatla, and Don Scansen, came up with a list of top challenges for the 22-nm node. Research firm Semiconductor Insights is part of United Business Media (UBM), which also owns EE Times.
Here's a list of 15 challenges (and more):
1. Cost and affordability
Cost of research and development, process technology, design-for-manufacturing (DFM) and other pieces of the IC-production puzzle continue to soar. Here's the big question: Do product volumes support the economic equation?
Scaling is nearing the limit. So do we start changing the channel material? So far, a lot of work is done outside the channel, thereby keeping it pristine. Many are looking at germanium for the channel, which has a lot of potential for the required bandgap.
New technologies like extreme ultraviolet (EUV) and maskless electron-beam lithography will not be ready for production. 193-nm immersion lithography will be extended to 22-nm with the help of double patterning.
4. Transistor architecture
Planar devices will likely be extended to 22-nm. Multi-gate MOSFETs like Intel's tri-gate transistor and IBM's FinFETs have significant challenges with parasitic capacitance, parasitic resistance, among others.
5. Bulk silicon or silicon-on-insulator (SOI)
Bulk vs. SOI? No clear favorite for 22-nm--yet. Maybe both will be used.