Top 15 technology challenges for 22-nm node

Replacement gate integration approach will be challenging due to narrower gate lengths. Zirconium oxide will be required for the scaling down of equivalent oxide thickness (EOT).

7. Strain technology

Various technologies, including stress memorization techniques (SMT) and tensile stress liner, have been used and embedded Si-C may be needed to improve NMOS current drive. Embedded silicon germanium (SiGe), compressive stress liner and channel/substrate orientation will be needed to boost PMOS performance.

8. Interlayer dielectric

Ultra low-k dielectric or air gap technology will be required as well as new barrier materials for copper. Further reduction of ''K'' value from 2.6 to 2.2 will be necessary to reduce coupling capacitance. Porous carbon-doped oxide materials will be needed.

9. Ultra shallow junctions for NMOS and PMOS

Ion implantation, coupled with flash and spike anneal, will be required.

10. Advanced liner for copper interconnect

Advanced liner and capping layer will be needed to improve the performance of the copper interconnect.