Lithography hit by R&D gap, downturn

Double trouble
Supporters of EUV, maskless and nano-imprint disagree with those assessments, saying they will be ready for the 22- or 16-nm nodes. Until then, leading-edge chip makers must resort to double patterning. At present, leading-edge chip makers are using 193-nm immersion technology for 45-nm chip production. Some are also using a combination of OPC, phase-shift masks and double-patterning.

Amazingly, optical lithography continues to defy the law of physics. 193-nm immersion can be extended to the 15-nm node (22-nm half-pitch logic), thanks in part to double patterning, said Burn Lin, senior director of the micropatterning division at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Lin is considered the innovator behind immersion, it was noted.

In doubling patterning, an IC maker is essentially doubling the process steps and creating two masks, thereby boosting production costs. There are also various flavors of doubling pattering: LLE, LELE, spacer and others.

Litho-litho-etch (LLE) may be cheaper than the rival litho-etch-litho-etch (LELE) method, but LLE uses newfangled processes that are somewhat unproven. LLE uses two lithography exposures and two resist layers to create smaller IC features. In comparison, LELE uses two lithography exposures and hard-mask etches to create smaller features.

A third method is called spacer or self-aligned double patterning. ''Spacer is a double patterning technique that uses deposition, anisotropic (directional) etching and trimming to produce smaller features on chips,'' according to ASML Holding NV.

Leading-edge chip makers may use one or more types of schemes, depending on the product type. So far, the most desirable technology is LLE, due to fewer process steps and cost.

TSMC's Lin said he prefers LLE, ''because of cost.'' The NAND flash crowd, which is said to be leading the process technology race, is already deploying some form of a double patterning scheme, reportedly spacer or sometimes called self-aligned double patterning.

The DRAM community, which is lagging in process technology, is evaluating spacer and LELE, analysts said. On the processor side, it appears none of the candidates are terribly attractive due to cost and complexity.

LELE ''is expensive,'' said Jongwook Kye, principal member of the technical staff at Advanced Micro Devices Inc. For spacer, ''Applied (Materials Inc.) has some solutions, but it's not perfect. Spacer is great for very regular designs.''