Sematech appears to have taken a hybrid approach to the problem by disclosing what it called a ''via mid'' technology. The technology appears to resemble a via first approach, in which the vias are produced in the front end of the process.
In via mid, according to Sematech, the fab produces the CMOS device and TSV. The fab or packaging house handles many of post processing steps, such as the bump, probe, back grinding and others. Then, the packaging house handles the final test.
In recent times, Sematech has been lining up equipment suppliers for its efforts in the 3-D arena.
Recently, Sematech said that Atotech Inc. has become a member of its so-called 3D Interconnect Program located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. Sematech and Atotech will collaborate in research to enable the development of copper electroplating solutions that will enable void-free filling of high density 3-D TSVs.
Another vendor, Nexx, has recently joined the effort as well. The fab tool firm will collaborate with Sematech in leading-edge research on innovative electrodeposition technology and the development of high-yield, low-cost copper electroplating solutions that will enable high-density TSVs.
Sematech has also recently received a 300-mm Telius SP UD system from Tokyo Electron Ltd. (TEL). The system is an etch tool for TSVs. Rudolph Technologies Inc. also recently joined Sematech's 3D Interconnect Program. Rudolph's inspection and metrology technologies will be applied to various projects including via depth and CD metrology, metallization void detection, stacked wafer via alignment, wafer edge defect detection and bump height coplanarity.
To gain a better understanding of how new and existing wafer metrology technologies can be used, Sematech will host a workshop dedicated to 3-D interconnect metrology on July 15 in conjunction with Semicon West in San Francisco.