Five enablers for future chip scaling

To enable chip scaling, there is always brute-force lithography. During a presentation on Friday (June 26), chip-making consortium Sematech outlined other and futuristic ways to enable Moore's Law.

Here are some of the proposed options from Sematech for transistor-level scaling in the near future and beyond:

1. Zero low-k interface. In current 45-nm designs from Intel Corp., there is the silicon substrate and the high-k/metal-gate scheme. A low-k material sits between the silicon and high-k structure. But with a zero low-k interface, the low-k material is removed, enabling more drive current and less leakage. This is an option for the 16-nm node or sooner.

2. Single metal gate stack. Instead of a traditional transistor, a high-k/metal-gate scheme makes use of a single metal gate stack. This improves the performance but lowers the power consumption of the device.

3. Gate stacks on III-V semiconductors. Intel, Sematech and others have talked about using an InGaAs/high-k interface for future designs. Would also boost performance and lower power.

4. Quantum-well MOSFETs. The use of silicon-germanium on silicon as a means to boost performance. Intel recently demonstrated a high-speed, low-power quantum well field effect transistor. The p-channel structure will be based on a 40-nm indium antimonide (InSb) material.

5. 3-D chips using through-silicon-via (TSVs). Sematech on Friday disclosed plans to set up a 300-mm R&D ''test bed'' for the production of 3-D devices based on TSV technology.