TSMC's Reference Flow 10.0 addresses new design challenges at 28-nm and includes innovations to enable system-in-package (SiP) design, according to TSMC (Hsinchu, Taiwan).

New to the flow is an RTL-to-GDSII chip implementation track from Mentor Graphics Corp., TSMC said. Other EDA partners in the flow include Synopsys Inc., Cadence Design Systems Inc. and Magma Design Automation Inc., TSMC said, as well as Altos, Anova, Apache, Azuro, CLK DA, Extreme DA, and Nannor.

TSMC said it proactively engaged EDA ecosystem partners in creating the new methodology upon the introduction of its 28-nm process technology. For Reference Flow 10.0, TSMC said it went beyond physical verification of design rule checking (DRC), layout-versus-schematic (LVS) and extraction tools and engaged early collaboration with EDA partners to bring their place-and-route tools up to speed with the foundry's 28-nm process.

Reference Flow 10.0 introduces SiP design solutions for the first time, TSMC said. SiP solutions in the flow range from SiP package design, electrical analysis of package extraction, timing, signal integrity, IR drop, and thermal to physical verification of DRC and LVS, according to the company.

New low-power features associated with Reference Flow 10.0 include support for pulsed latch, a new low-power implementation scheme for power saving and hierarchical low power automation, multi-corner power/timing co-optimization, multi-corner low power clock tree synthesis, vectorless power analysis and more, enabling more effective power-aware implementation and power analysis, TSMC said.

To drive greater performance, advanced stage-based on-chip variance optimization and analysis is made available for the first time, enabling customers to get a more realistic look at timing for the purpose of removing redundant design margins, TSMC said.

The flow also includes a new electrical design-for-manufacturing (DFM) feature enabling customers to take into consideration the timing impact of silicon stress effects, helping to increase yields, TSMC said.

TSMC Tuesday rolled out an interoperable custom IC design kit and two unified EDA data formats.