DAC preview: Power again takes center stage

Designers are taking even more dramatic steps to combat leakage at the advanced nodes, according to Mark Throndson, director of product marketing at IP provider MIPS Technologies Inc. "We're seeing a great amount of interest in solutions for reducing leakage power in our multicore products through solutions like dynamic core shutdown," he said.

Since dynamic power is proportional to the voltage squared, designers are focusing more on using multiple voltages and multiple voltage domains in their designs, said Barry Pangrle, a solutions architect for low power design and verification at Mentor Graphics Corp. Portions of the design now must operate in multiple modes (drowsy, sleep, active, turbo) where the voltage and clock frequencies are tailored to be as energy efficient as possible while simultaneously delivering the performance necessary for that given mode, he said.

"In cases where a portion of the design's functionality isn't needed, the power can be shut off to further reduce the leakage power," Pangrle said.

Power has become an intricately interwoven element of the design closure process, a multi-faceted challenge that becomes more daunting at the 40- and 32-nm nodes, according to Steve Carlson, vice president of marketing for front-end design at Cadence Design Systems Inc.

Exacerbating this is the more prominent role of analog content in advanced designs, Carlson said.

"Most advanced node designs are aimed at high-volume applications that require significant analog-functional content. The interlock of all these aspects of design is really the crux of the challenge of today's design teams," Carlson said. "The solution must be rooted in a holistic approach that brings together the design process, the closure criteria, the underlying infrastructure and the ecosystem."

Still another challenge in the realm of power is that, since low-power designs tend to have a poor signal-to-noise ratio, maintaining reliable system operations becomes more challenging, said Nhat Nguyen, a senior engineering manager at memory IP vendor Rambus Inc.

Choosing process technology

Leakage power is of course highly dependent on process technology. Mentor's Pangrle noted that foundries typically have multiple offerings at a given technology node, ranging from slower transistors with better leakage power characteristics to faster, more power hungry transistors.

The adoption of high-k/metal gate process technology and advanced strain processes bring some relief on leakage issues, but do not totally solve the problem, according to Pangrle. "Silicon vendors that haven't mastered these process techniques are at a disadvantage to those who have," he said.

Intel Corp. has been using high-k metal gate process technology since the 45-nm node. Taiwan Semiconductor Manufacturing Co. Ltd. plans to use high-k at the 28-nm node. IBM Corp.'s "fab club" plans to deliver a 32-nm process incorporating high-k and metal gate technology later this year. GlobalFoundries Inc., the foundry spin-off of Advanced Micro Devices Inc., plans to plans to ramp a 32-nm process based on SOI and a high-k/metal-gate scheme in the first quarter of next year.