Researchers: Ferroelectric DRAM smaller, faster than flash

Ferroelectric materials also dovetail with current trends in advanced transistors, in particular with the use of high-k dielectrics. CMOS transistor sizes are limited by the thickness of their gate oxides, which are approaching the atomic scale. To scale below 32 nanometers, semiconductor makers have had to switch to high-k dielectrics to prevent gate oxides from getting too thin.

Ferroelectric materials are even higher-k materials than the dielectric used in today's transistors, offering a clear path to advanced processing nodes, according to Yale an SRC.

"Ferroelectric materials have a 'k' [relative dielectric constant] of least 100 compared to about 20 for other high-k dielectrics, enabling our design to scale five times further," Ma claimed. "The downside is that semiconductor makers have traditionally been afraid of ferroelectric materials. However, now that they have gained some experience with using high-k dielectrics, there won't be as much resistance." Yale's FeDRAM bit cells also are simpler than traditional DRAM bit cells, which require an extra component (a capacitor) to store a charge. FeRAM bit cells consist of a single CMOS transistor with its gate oxide replaced with a high-k ferroelectric material for storage.

"Their No. 1 advantage is the retention time of a FeDRAM, which is improved about 1000 times over conventional DRAMs, which means that refreshing can be done much less frequently," said Kwok Ng, SRC's director of device sciences. "The second advantage is scaling: In a normal DRAM the capacitor has to be big enough to hold the charge, and consequently takes up most of the area, which makes it very hard to scale. But there is no capacitor in a FeDRAM bit cell, so it is much easier to scale down to smaller sizes."

The third advantage, according to Ng, is power consumption during read/write operations. The researchers report a 20-fold decrease since no DC current was required to transfer the charge to the capacitor. DRAMs must pump a charge onto the storage capacitor. FeDRAMs can use a simple AC voltage potential to polarize the gate dielectric.

Rather than accumulating charge, FeDRAMs work by memorizing a shift in threshold voltage, which is the same principle used by flash memory to store multiple bits per cell. This is one of the directions Yale and SRC researcerhs plan to explore next.

The researchers also designed arrays, and will demonstrate working FeRAM arrays next year. So far, preliminary tests indicate that as many as 1 trillion read/write cycles are possible for FeDRAMs, but characterization of long-term reliability msut still be documented.