More kudos for Power7
PALO ALTO, Calif. Sun Microsystems claimed a new watermark for server CPUs, unveiling Rainbow Falls, a 16-core, 128-thread processor at the Hot Chips
conference Tuesday (August 25). But analysts gave the IBM Power7 kudos as the more compelling achievement in the latest round of high-end server processors.
Power7 packs as many as 32 cores supporting 128 threads on a four-chip module with links to handle up to 32 sockets in a system. "It is scaling well beyond anything we've ever really seen before," said Peter Glaskowsky, a technology analyst for Envisioneering Group (Seaford, NY).
Glaskowsky was quick to point out the two chips target very different markets. Sun aims at Web servers that cost tens of thousands of dollars while IBM targets "monstrously large databases where you need a single memory image," he said.
Indeed, IBM revealed it will use Power7 as a building block for the high-end supercomputer it is building under contract to the Defense Advanced Research Projects Agency. Cray is competing with IBM in a final phase of that project.
Both the IBM and Sun designs max out by supporting up to 128 threads in a single socket. However, IBM's Power7 has built in significantly more memory and bandwidth than Sun's Rainbow Falls to support IBM's big database customers.
Power7 includes 32 Mbytes in embedded DRAM in L3 cache alone. The chip also sports 590 Gbytes/second total chip bandwidth including two four-channel memory controllers per die.
IBM's Power7 packs eight cores and 32 Mbytes eDRAM on a die.
Click on image to enlarge.
By contrast, Sun's design—focused on raw thread throughput for Web servers—does not even use a level three cache. However, Sun is expected to adopt L3 cache in future chips.
IBM can configure its L3 cache in chucks that include private, local caches, shared caches and duplicated caches placed close to cores expected to need them/
In terms of on-chip interconnects, Power7 uses a hybrid ring and crossbar approach, although IBM did not detail the interconnect. Rainbow Falls uses a hierarchy of two crossbars with two cores sharing a link to the first-level crossbar.
"They are really force feeding their cores through those crossbars," said James Kahle, who led the IBM Cell processor design before heading up the Power7 effort.
IBM will make versions of Power7 with four, six and eight cores. They will fit into a similar power consumption envelop as the Power6, believed to range from 100W to 190W.