Updated: Researchers present MRAM-based FPGA architecture

PARIS — PARIS — Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed they have developed a FPGA circuit based on non volatile resistive memory cell.

In a discussion with EE Times, Lionel Torres, head of the microelectronics department at LIRMM and project leader, highlighted the ins and outs and laid down the foundations of future research projects.

Torres explained that the current technology used is Thermally Assisted Switching (TAS)-MRAM with a small current for heating the Magnetic Junction Tunnel, allowing a higher sensitivity to magnetic fields. The magnetic field is induced by a current line above or below the junction depending on the technology.

He noted:"The main advantage to use TAS in comparison to field-induced magnetization switching (FIMS) is that the current needs to induce the magnetic field are divided by two (between 5 to 10mA). It is clear that for power consumption the best solution is STT. Our cell also supports STT, it will certainly the next patent."

Torres continued: "Most FPGAs are currently SRAM-based. In these devices, configuration memory is distributed throughout the chip. Each memory point has to be readable independently because each of these points is used to drive a transistor's gate or a Lookup table (LUT) input. Nevertheless, for writing operation, the configuration memory is organized as a classical memory array. Speed limitation of the configuration is linked to the size of the words that the memory can write at a time. Multiplying the number of memory arrays can reduce this time and allows parallel loading of the configuration bit stream with partial dynamic reconfiguration capabilities."

According to Torres, the possibility to stack the MRAM over the CMOS logic in a single chip and to store permanently without power the configurations in Non-Volatile Magnetic FPGAs (NVM-FPGA) dramatically simplifies the system level design and integration into the final product. NVM-FPGAs do not require configuration loading at power-up or brown-out detection strategies in power glitch situations. No need to load the FPGA from the MCU at power-on and no additional power management circuitry to source, layout, debug and test.

The use of non volatile memories such as MRAMs helps to overcome the drawbacks of classical SRAM-based FPGAs without significant speed penalty, Torres added. Besides its advantage that lies in power saving during the standby mode, it also benefits to the configuration time reduction since there is no need to load the configuration data from an external nonvolatile memory as is usual in SRAM-based FPGAs. Furthermore, during the FPGA circuit operation, the magnetic tunneling junctions can be written allowing a dynamic (or shadowed) configuration and further increasing the flexibility of FPGA circuits based on the MRAM. On the other hand, MRAM memories have shown interesting features that include high-timing performance, high-density integration, reliable data storage, good endurance, and low number of additional masks required for the magnetic post process.

Torres then declared: "Another application we are looking at is the design of non volatile register that could be interesting for the MCU market. For example, if a MCU is based on non volatile register we can easily imagine saving the context of an application in only a few cycles. It is also a way to have products naturally robust against SEU. MRAM are not sensitive to SEU and we can use them to store and reuse sensitive data."

Torres said a testchip is currently under process, specifying that the CMOS part has been validated while the magnetic part is under process. This testchip, he added, is only a set of basic blocks to evaluate the performances and especially the power consumption. The first testchip has been made in CMOS 0.35µm with magnetic junction in 350nm too.