Atmel will fly with Sparrow
The Cortex A5 resides well below the performance and the power consumption of any Intel Atom chips. It is also significantly above ARM's M series that is increasingly gaining traction in the even broader market of microcontrollers for embedded systems
The Cortex A5 essentially is a simplified version of the A8/9. ARM took the superscalar pipeline capable of issuing multiple instructions per clock cycle and trimmed it down to a pipeline that basically issues one instruction per clock handled in order.
However, the A5 does have a dynamic branch prediction capability that gives it better performance than the ARM9. It also has a capability to issue two instructions in limited branching situations, said Travis Lanier, product manager for the A5.
In a low power 40 nm process, the A5 is expected to run at data rates up to about 500 MHz, burn about 0.12 milliW per MHz and deliver about 1.57 Dhrystone MIPS per MHz. Data rates could be doubled using a general purpose process technology, although that is not the chip's main target.
The net result is a core that could provide about 20 percent more performance than an ARM11 at two-thirds its area and 80 percent more than an ARM9 in a similar size chip.
ARM simplifies Cortex pipeline with A5 "Sparrow"
Click on image to enlarge.
The core also shares a lot of the technical goodies of its big brothers, the Cortex A8 and A9, which the older ARM cores lack. For instance the A5 supports ARM's Neon SIMD instructions for media acceleration and its TrustZone security capabilities.
The new core also supports the ARM 64-bit AXI bus. However, many chip makers are expected to continue to use existing peripherals on the 32-bit AHB bus except for a few blocks that demand higher performance.
The A5 can also use ARM's Mcore technology to be implemented in a quad-core processor. Such a design could run at up to a GHz and deliver 8.5 CoreMarks per MHz, ARM claims.
ARM is still finishing the A5 design and doesn't expect to have test chips back from the fab until early next year. The company is believed to have three A5 licensees, led by Atmel, which decided at the last minute to hold an announcement until it was closer to the release of silicon.
According to documents obtained by EE Times, Atmel is expected to announce in the second half of 2010 a single-core A5 chip built in a 65nm process and running at 667 MHz to deliver 1,000 Dhrystone MIPS. The processors will be C code compatible with the Atmel's existing ARM926 chips, likely support two DMA-backed DDR2 memory channels and use a combination of the AXI and AHB buses. They will take on Mips, PowerPC and x86-based processors in a variety of industrial, medical and retail markets.
The A5 has plenty of head room for more licensees given ARM has more than 100 ARM926EJ-S and more than 40 ARM1176JZ licensees. But it's still early days. Given the early stage of the design, most chips based on the core may not ship until 2011.
"They are trying to move people up to the Cortex line which has features the older cores lack," said Tom Halfhill, senior editor of the Microprocessor Report. "The ARM11 is about five years old while the 926 is about nine years old, and--even for embedded processors--that's a long time," he said.
"To some extent this will help ARM defend its markets from encroachment from Intel and others," Halfhill added. "Its way below the neighborhood of the Atom, but Intel is going in this direction," particularly with its deal in March to make the Atom core available through TSMC, he said.