News & Analysis
Researchers detail new power management technique
Dylan McGrath
11/2/2009 5:15 PM EST
The scheme, dubbed shared recovery technique, was the subject of a paper presented at the International Conference on Computer-Aided Design (ICCAD) Monday (Nov. 2) by Baoxian Zhao, a computer science graduate student at George Mason University.
According to the paper, the main thrust of the shared recovery technique is the designation of a global shared recovery block with a design that can be used by any task at run time. Simulation results show that the technique can achieve up to 35 percent energy savings when compared to existing reliability-aware power management schemes, according to the paper.
Zhao noted that dynamic voltage scaling remains a wildly popular technique for energy management in embedded applications. But, he said, recent research demonstrates that dynamic voltage scaling has a significant negative impact on system reliability.
Zhao co-authored the ICCAD paper, titled "Enhanced Reliability-Aware Power Management through Shared Recovery Technique," along with Hakan Aydin from George Mason and Dakai Zhu from the University of Texas at San Antonio.
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Nirav Desai
11/4/2009 6:54 AM EST
Multi Core Processor Designs are currently the state of the art in processor design, with some having as many as 100 cores in them . These offer record breaking throughput with power consumption reaching 55 Watts.
On the other side are mobile processors for laptops and netbooks and embedded processors, increasingly being found in hand held devices like the iPhone, where power consumption is the main bottleneck in achieving higher processor speeds.
What if we marry the two concepts together, to make a dual core embedded processor, with one low power core and another high power. The low power core does all of the usual work once the cache / RAM is fully loaded and the high power core idles at this time - giving the power consumption of a single core processor for most of the running time. In case an instruction asks for information not on the Cache / RAM, the high power core can be kicked into action to do the needful..
Haven't read of such a design till now..most of the power management schemes involve dynamic voltage scaling, which has its own reliability concerns. What do you think would be the drawbacks of such a design ? Do you think this kind of procesor design can be successful ?
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DashawnX
11/7/2009 4:45 AM EST
Multi Core Processor Designs are currently the state of the art in processor design, with some having as many as 100 cores in them. These offer record-breaking throughput with power consumption reaching 55 Watts. On the other side are mobile processors for laptops and netbooks and embedded processors, increasingly being found in hand held devices like the iPhone, where power consumption is the main bottleneck in achieving higher processor speeds. What if we marry the two concepts together, to make a dual core embedded processor, with one low power core and another high power. The low power core does all of the usual work once the cache / RAM is fully loaded and the high power core idles at this time - giving the power consumption of a single core processor for most of the running time. In case an instruction asks for information not on the Cache / RAM, the high power core can be kicked into action to do the needful. Haven't read of such a design till now, most of the power management schemes involve dynamic voltage scaling, which has its own reliability concerns. What do you think would be the drawbacks of such a design? Do you think this kind of processor design can be successful even without using any href="http://personalmoneystore.com/Short-Term-Loans/short-Term-Loan ">short term loan?
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