Dublin lab lays groundwork for Intel's nanotech future

LONDON — Back in 1994, Leonard Hobbs, now process engineering department manager and research programs manager for Intel Ireland, helped transfer a 0.5-micron CMOS process to Dublin, making Fab 10 Intel's most advanced wafer facility when it opened that year. Today, the 19-year Intel veteran oversees the company's European nanotechnology research program.

Hobbs points out that the research is predominantly precompetitive and as such tends to look forward five to 10 years. As technologies come closer to deployment, they get passed back to Portland, Ore., where Intel tends to pursue development behind closed doors.

Intel has tried to leverage the efforts of its researchers by sponsoring research at universities and cooperating with European research institutes. "Six or seven years ago, the Science Funding Ireland initiative was started by the government in an attempt to attract Irish professors back to Ireland. We took advantage of that and got involved," said Hobbs.

Much of Intel's nanotech research is done with the Center for Research on Adaptive Nanostructures and Nanodevices (CRANN) at Trinity College Dublin and at the Tyndall Institute in Cork. As a result, nine Intel researchers working out of Ireland can have a multiplicative effect and help influence the direction of academic research for Intel's benefit, Hobbs said. The collaborative work also helps Intel uncover promising nanotech talent for possible recruitment.

As for the work itself, "we don't think much about [development] this side of 10 nm," he said, since "32 nm is already out there, 22 nm will appear in 2011, and they are already working on 16 nm in Portland."

Hobbs sees the major challenges as the continuation of patterning by self-assembly and lithography; the metallization challenge--how, and whether, copper scales, and its possible replacement with carbon; and the possible replacement of silicon itself with higher-mobility material, such as indium gallium arsenide, in the transistor channel.

"Low-k material is also a challenge for the back end," said Hobbs. "We keep our eye on silicon and related materials such as III-Vs. Self-assembly and the movement of individual atoms are also key. Carbon is an area of interest because copper becomes difficult to work with. For copper, the resistance goes up at smaller dimensions, and the laying down of liners and barrier layers becomes problematic."

Much of Intel's carbon work is being done in collaboration with CEA-Leti in Grenoble, France, while participation in the European Nanoelectronics Industry Advisory Council has led to Intel's role in a European consortium looking at the transition to manufacturing ICs on 450-mm wafers.

In general it is recognized that device structures and shapes will be different by the time manufacturing gets to the 11-nm process node. But Hobbs said devices are Portland's domain. Although some research must be done with cognizance of the structure, in general the kind of pure material measurements that Intel's European team is making don't need to know the structure.

"Eventually" noted Hobbs, "the device becomes a wire anyway."

See also:
Europe betting on payout from Intel Labs' gambit
Tech transformation prescribed for geriatric health care