In a paper at the International Solid State Circuits Conference (ISSCC) IBM described what it calls a wire-speed processor. The 45nm SOI chip is built up from a number of accelerators and 16 cores based on a new 64-bit embedded PowerPC processor capable of handling four threads.

"This is probably the most complex chip IBM has ever built in its history," said Charles Johnson, chief architect of wire-speed processors at IBM.

Charles Johnson Chief Architect, Wirespeed Processors, IBM

The 16-core chip packs 1.43 billion transistors into a 428mm-squared die. By contrast IBM's high-end server CPU, the eight-core Power7, puts 1.2 billion transistors in a 567mm-squared die.

"We realized this might be more complex than Power7 when the IBM fab people start telling us our masks were so hard to build, so we started counting the transistors on the chip," Johnson said.

Unlike the Power7 which aims at highest performance, the wire-speed processor is aimed at highest throughput per Watt. Versions of the chip may span a range from 2.3 GHz 16-core chips consuming 65W to four-core versions at 1.4 GHz consuming 20W.

Johnson said the chip stands in between a multicore server processor like Sun Microsystem's Niagara and a more conventional packet processors from companies such as Cavium Networks or RMI.

"It's not a network processor or a server processor but a middle ground, a blurring of the two worlds," Johnson said.

The chips will be used in a range of standalone systems and PCI Express adapter cards in servers. It is mainly designed for use in IBM's own systems, however the company is willing to sell it on a merchant basis as well.

Johnson declined to detail applications for the chip, deferring to an issue of an IBM Research journal coming out in about a month. He did say IBM's software division has worked closely with the processor team.

"Wire-speed processors are an extreme example of workload-optimized computing," Johnson said.

Bigger than a PC server CPU
"Basically it sounds like a high-end ASIC along the lines of what Cisco Systems develops for its routers and switches," said Linley Gwennap, principal of market watcher The Linley Group (Mountain View, Calif.).

While the power consumption is in line with existing server and network processors, the die size is not, he added.

"That's a huge chip, bigger than most of the PC and server processor Intel makes and probably twice the size of many network processors out there, so cost-wise it will be tough for them to be competitive," Gwennap said.

"I don't see where they are getting something significantly better than using a merchant chip," he said. "The good thing for IBM is it leverages their PowerPC infrastructure and software rather than using a MIPS-based chip from Cavium or NetLogic," Gwennap added.

Johnson said IBM has been working on the concept for five years. The first two years IBM Research worked on concepts around extreme multicore processors and emerging workloads. About two years ago that work became a product concept involving members of IBM's chip, systems and software groups.

The chip contains an XML accelerator as well as a regular-expressions processor and several crypto accelerators. It runs a Linux operating system and supports a Linux hypervisor to virtualize all I/O, processor and memory elements.

The chip taped out about a week ago. First silicon is expected in about two weeks for testing in already completed systems designs.

Johnson said the design could easily scale from processing 10 to 100 Gbit Ethernet workloads by adding with new process generations more of the existing core and accelerator blocks.

Up to four 16-core chips can be linked in a symmetric multiprocessing system without needing additional bridge chips. Each processor supports up to 8 Mbytes cache and four 10G Ethernet ports.

Johnson was chief architect of IBM's Power4 processor. He also designed IBM's portion of the processor in the Microsoft Xbox 3609 videogame console.