IEEE publishes 1149.7 test standard for on-chip testing

MANHASSET, NY — IEEE has published the IEEE 1149.7 test and debug standard, which expands the 1149.1 JTAG standard's functionality while maintaining previously made industry investments.

The standard, which was ratified in December 2009, was espoused by Texas Instruments, which was instrumental in working out the original 1149.1 standard.

"IEEE 1149.7 offers a flexible, dynamic solution for designers and engineers contending with shifting design paradigms without eroding the firm foundation established by earlier standards, such as IEEE 1149.1," said Stephen Lau, emulation technology product manager, Texas Instruments.

"Any integrated circuit using the IEEE 1149.1 interface may use this standard to reduce the test interface pin count from four or more to two, while at the same time providing more advanced capabilities," said Rob Oshana from Freescale Semiconductor, chairman of the IEEE 1149.7 working group.

The IEEE 1149.7 standard addresses complex digital circuitry, form factor size constraints, and multiple CPUs found today's smaller size consumer electronics.

The six classes (T0 " T5) contained within the standard include IEEE 1149.1 extensions.

New features include:

decreased scan chain lengths

four selectable power modes

two-pin operation

chip bypass and star topology testing

background data transfers concurrent with advanced scan transactions