News & Analysis
3-D architecture promises new type of PLD
Dylan McGrath
3/1/2010 6:01 AM EST
According to Tabula executives, the company's Spacetime architecture rapidly reconfigures to execute portions of a design in a series of steps. Compared with a 40-nm FPGAs, Tabula's 40-nm devices will offer more than twice the logic density, twice the memory density, nearly three times as many memory ports and four times higher DSP performance, they claim.
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| Dennis Segers Tabula Inc. |
Segers and Steve Tieg, Tabula's president and chief technology officer (CTO), said 3PLDs use time as a third dimension, reconfiguring on the fly at multi-gigahertz rates, executing each portion of a design in an automatically defined sequence of steps. Tabula's devices include multiple layers, which the company calls "folds," in which computation and signal transmission occurs. By rapidly reconfiguring to execute different portions of each function, a 3-D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an FPGA, according to Tabula (Santa Clara, Calif.).
"Assuming it works as they say, it's impressive. It's very impressive," said Rich Wawrzyniak, an analyst with Semico Research Corp. Wawrzyniak said Tabula would still face the issues common to all programmable logic startups, including lack of an established track record and the performance and ease-of-use of its development tools.
Startups in the programmable logic business have historically faced an uphill climb. More than 50 companies have attempted to play in the space since it was established in the early 80s. Most of them essentially failed. Since the late 80s the market has been dominated by two suppliers—Xilinx Inc. and Altera Corp.
Veterans of the industry—including the executives at Tabula—acknowledge that many startups failed because they offered technology and development tools that were so fundamentally different from what users where accustomed to that they failed to gain traction. Tabula is offering a radically different technology—but Segers and Tieg say the dramatic differences in the architecture are transparent to the user. The user experience of Tabula's development tools is also consistent with what designers have grown used to, they said.
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| Steve Tieg Tabula Inc. |
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Caincom
3/2/2010 12:33 PM EST
Failure of so many roconfigurable architectures seems to be about finding the right technology, educating the potential customers and strong, strong marketing more than about the specific architecture. This approach sounds a lot like Chameleon and they couldn't convince the users
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Sundar Srinivasan
3/2/2010 3:05 PM EST
The startup companies that introduce new reconfigurable architecture have a difficult time, because it's potential customers have established processes for existing technology that this new technology does not readily map to. Nobody wants to change the process. So unless these companies also offer the entire array of CAD tools to program their fabric, they may not succeed.
http://sunnyeves.blogspot.com/
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schaferb
3/3/2010 2:54 AM EST
With all the respect, but is this not a dynamically reconfigurable FPGA that NEC electronics already commercializes and calls it STP (stream transpose processor)?
(http://techon.nikkeibp.co.jp/article/HONSHI/20081230/163439/)
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SOY
3/5/2010 9:45 AM EST
I'd like to write about architecture side and performance at first.
The 3DPLD is probablly same as DPGA (in general, called multi-context FPGA) researched by Prof. A.DeHon (when he was PhD @ MIT, and currentlly he is in Penn Univ) who is one of evangelists of reconfigurable computing. At the same time (maybe 1996-97), Xilinx researcher also proposed time-multiplexed FPGA, moreover, earlly in 90s, Fujitsu got Patent for the multi-context approach. Developping architecture is easy, but how to schedule the context (task) is difficult for dynamically changing the context without deadlock and so on. I remember that some researcher has proposed such "3D placement" that 2D field of programming + time domain at previous decades.
At view point of performance on chip-level not inside of it, throughput is decreased by the number of contexts, of course. And the dynamically changing is OVERHEAD on space and time in general, and thus breaking data-flows on the chip. Researchers want not to make dynamically change, so device is treated as possible as static device even if a device can change dynamically, in order to reduce the overheads. Some researcher concluded, "we must find killer application to use the dynamically change (thus reconfiguration) effectivelly". Unfortunatelly, such application is not yet found, time is past (one decade at least). In addition, I think key is how to use an inter-configuration communication proposed by B.Hutching (Prof. @ BYU).
Regarding marketing side,
3D or DPGA must claim about application designers need not familiar with the device or its system, this means the device have to support or include current design process. So, the design tool will be more complex, or more tool-chains is necessary, probablly taking more time. Application designers face to time-to-market issue, no choice if it is not possible. So, not only killer application, but also traditional application should be enhanced at the design time or performance perspectives.
Regards,
SOY
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green_is_now
12/19/2012 8:04 PM EST
how will this technology be ranked in terms of security with this alway reconfiguring and re-using paradimes?
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