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3-D architecture promises new type of PLD

Dylan McGrath

3/1/2010 6:01 AM EST

In addition to offering a compelling technology, Tabula also boasts a an experienced management team. Tieg, who founded the company, is considered a pioneer in EDA and was the CTO at Cadence Design Systems Inc. and three other firms. Segers is 33-year veteran of the semiconductor industry who was CEO of Matrix Semiconductor Inc. and a long-time executive and later board member at Xilinx. Several other Tabula executives, including Vice President of Hardware Development Matt Crowley, Vice President of Manufacturing Technology Daniel Griffin, Vice President of Software Development Rajeev Jayaramen, Vice President of Marketing Alain Bismith and Vice President of Sales Steven Haynes, also have impressive resumes, many with Xilinx or Altera.

Given the experience of Tabula's management team, Wawrzyniak said the company could have the direction to steer clear of the traps that have befallen many of its predecessors. "They know those pitfalls very well," he said. "I expect them to be able to navigate around them."

Tabula plans to initially target the market for high-end programmable logic devices (PLDs). But the company foresees broader applications for its technology and thinks it could eventually be a market leader in programmable logic. "We think we have what it takes to make that happen," Segers said. He added, "I think we can take PLDs into markets that FPGAs can't penetrate."

"We have every intention of penetrating a wide variety of markets," Tieg said.

Tieg founded Tabula in 2003. The company has more than 100 employees and has raised some $106 million in venture capital backing. The company has filed for some 150 patents, more than 80 of which have been granted, according to company executives.





Caincom

3/2/2010 12:33 PM EST

Failure of so many roconfigurable architectures seems to be about finding the right technology, educating the potential customers and strong, strong marketing more than about the specific architecture. This approach sounds a lot like Chameleon and they couldn't convince the users

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Sundar Srinivasan

3/2/2010 3:05 PM EST

The startup companies that introduce new reconfigurable architecture have a difficult time, because it's potential customers have established processes for existing technology that this new technology does not readily map to. Nobody wants to change the process. So unless these companies also offer the entire array of CAD tools to program their fabric, they may not succeed.

http://sunnyeves.blogspot.com/

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schaferb

3/3/2010 2:54 AM EST

With all the respect, but is this not a dynamically reconfigurable FPGA that NEC electronics already commercializes and calls it STP (stream transpose processor)?
(http://techon.nikkeibp.co.jp/article/HONSHI/20081230/163439/)

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SOY

3/5/2010 9:45 AM EST

I'd like to write about architecture side and performance at first.

The 3DPLD is probablly same as DPGA (in general, called multi-context FPGA) researched by Prof. A.DeHon (when he was PhD @ MIT, and currentlly he is in Penn Univ) who is one of evangelists of reconfigurable computing. At the same time (maybe 1996-97), Xilinx researcher also proposed time-multiplexed FPGA, moreover, earlly in 90s, Fujitsu got Patent for the multi-context approach. Developping architecture is easy, but how to schedule the context (task) is difficult for dynamically changing the context without deadlock and so on. I remember that some researcher has proposed such "3D placement" that 2D field of programming + time domain at previous decades.

At view point of performance on chip-level not inside of it, throughput is decreased by the number of contexts, of course. And the dynamically changing is OVERHEAD on space and time in general, and thus breaking data-flows on the chip. Researchers want not to make dynamically change, so device is treated as possible as static device even if a device can change dynamically, in order to reduce the overheads. Some researcher concluded, "we must find killer application to use the dynamically change (thus reconfiguration) effectivelly". Unfortunatelly, such application is not yet found, time is past (one decade at least). In addition, I think key is how to use an inter-configuration communication proposed by B.Hutching (Prof. @ BYU).

Regarding marketing side,

3D or DPGA must claim about application designers need not familiar with the device or its system, this means the device have to support or include current design process. So, the design tool will be more complex, or more tool-chains is necessary, probablly taking more time. Application designers face to time-to-market issue, no choice if it is not possible. So, not only killer application, but also traditional application should be enhanced at the design time or performance perspectives.

Regards,
SOY

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green_is_now

12/19/2012 8:04 PM EST

how will this technology be ranked in terms of security with this alway reconfiguring and re-using paradimes?

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