Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

The key is that Tier Logic's 3-D TierFPGA features one level, or tier, of thin-film transistor (TFT)-based SRAM, creating a more efficient device than a traditional 2-D FPGA, a large percentage of which is configuration SRAM, according to Paul Hollingworth, a 23-year-veteran of the chip industry who serves as Tier Logic's vice president of sales and marketing.

Tier Logic's FPGA's are converted to ASICs by replacing the TFT SRAM top layer containing the programmable configuration circuitry with a simple metal layer, retaining the identical timing, according to the company.

But the biggest advantage of the device's structure is that it enables TierFPGAs to be converted to ASICs relatively quickly and painlessly by simply replacing the TFT SRAM with metal, according to Hollingworth. A former head of Altera Corp.'s HardCopy product line, Hollingworth said he joined Tier Logic because he recognized the potential of the technology to be "what HardCopy was supposed to be." While converting an FPGA to a HardCopy ASIC requires significant changes to the timing of a design, a TierFPGA can be converted to a TierASIC "much more seamlessly," according to Hollingworth.

Unlike any other type of ASIC conversion, the Tier Logic timing remains identical between the FPGA and ASIC, allowing zero-risk, zero-effort conversions, Hollingworth said. He said the company's "design once approach" delivers same-die silicon with identical functionality and timing for both FPGA and ASIC products.

Tier Logic was founded in 2003 Raminda Madurawe and Peter Suaris, veterans of Altera and Mentor Graphics Corp., respectively, according to the company. The company received seed funding in 2005. In 2007, the company announced it received Series A funding from investors Matrix Partners and Walden International. The company is headquartered in Santa Clara, Calif., but has about half of its employees in Colombo, Sri Lanka, the native country of Madurawe and Suaris.

TierFPGAs claim greater gate density compared to competing FPGAs by virtue of the 3-D architecture and higher logic efficiency from greater configurability, according to Hollingworth.

In terms of cost per density, TierFPGAs cost more than 50 percent less than high-end 2-D FPGAs and 20 percent less than low-end 2-D FPGAs, according to Hollingworth. Converting designs to TierASICs lowers costs by another 50 percent and costs less than $50,000 in non-reoccurring engineering costs, Hollingworth said.

Compared with a conventional approach, where converting an FPGA design to an ASIC requires a complete re-design and takes nine to 12 months, converting from TierFPGA to TierASIC takes only about four weeks, Hollingworth said.

Does not impose new methodology
Hollingsworth said that despite the dramatically different architecture, using Tier Logic's products does not impose a new methodology on users. "The architecture is very different, but the customer is not aware of that," Hollingworth said. "Any user is going to be able to perform design and debug in a perfectly standard way."

The company's Mobius tool flow performs back-end place and route, static timing analysis and other functions, offering the same features as existing FPGA providers and an identical design flow, Hollingsworth said. The tools are integrated with Mentor Graphics Corp.'s Precision synthesis tool to provide a seamless development environment, he said. The same tool chain can be used to produce both FPGAs and ASICs, he said.

The production release of the Mobius tools occurred in December 2009, following a successful beta testing phase, according to the company. The company plans four more releases of new versions of the tools this year—one per quarter.

Paul Hollingworth Tier Logic

As its foundry partner, Tier Logic is using Toshiba Corp. Hollingworth said Toshiba was "an interesting choice" because the company is the world's third largest semiconductor company and has a great deal of experience producing TFTs.

Hollingworth admitted that Tier Logic may have remained in stealth mode a bit longer if not for the attention generated by Tabula's recent launch. Tier Logic remains in its early stages—ready to take FPGA designs and convert them to the Tier Logic architecture, he said. For the time being, Tier Logic is willing to waive the NRE charges for conversion with production orders worth $50,000 or more. For a production commitment of $100,000, the company is also offering free pin-compatible package development. (More information about the offer is available to users who register through Tier Logic's website.)

So far, the 3-D TFT process technology has resulted in nine lots of TFTs and one fully integrated FPGA manufactured and measured, according to Tier Logic. The company's first TierASIC devices were received in September 2009, with all circuit blocks verified as functional, the company said. The first TierFPGA devices were received in December, the company said. The company said it plans to sample TierFPGA devices in the second quarter, with volume production planned for the fourth quarter.