Janac founded Silicon Navigator Inc. and Chip Estimate Corp. before forming Parallel Engines (Cupertino, Calif.) in April 2008 with the claimed intention of merging semiconductor IP and EDA into a single set of tools.

The company said it would deliver tools with bundled models for a new class of engineering desktop applications.

At one level the company is focused on chip floor planning but that also means being aware that most blocks in a system-chip will be sourced externally. Tools must not only be able to cope with physical IP integration but also have the functional knowledge to deal with 20-plus vendors contributing to a single design.

Design has moved above 70 percent IP block reuse, and the need to integrate many vendors in the supply chain into the design team has grown. The next few years will see the emergence of dominant IP vendors, with lines blurring: IP vendors providing EDA and EDA vendors providing IP. Janac's contention is that the EDA industry has been slow to embrace the internet- and browser-based tools.

Parallel Engines plans to launch a series of web sites to help designers access information on IP blocks while its IP-Integration desktop will reach out and gather supply chain data.

Parallel Engines' products include: Chip Planner, a downloadable tool for IP- and RTL assembly, floorplanning and timing/power evaluation; Chip Specification: Web-enabled tool for the capture of Chip Specifications. Produces documents that can be sent for quoting or directly imported into evaluation and floorplanning tools; IP Directory which is a library of more than 8,000 pieces of IP from more than 400 vendors; Physical RTL Evaluator is bundled into Chip Planner to help with evaluation of IP blocks.

The Dimensions Framework is the graphical desktop for hosting the Parallel Engines tools. The Dimensions desktop is a multi-treaded implementation in Qt 4, OpenGL, C++, and Python, hosting a multi-window environment for plug-in editors.

Related links and articles:

www.parallelengines.com

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