The Icyflex architecture was developed as a flexible processor with both DSP and control-type capabilities and C-compiler support, with a best-in-class power budget.

The Icyflex-1 is a 16/32-bit RISC processor for a mix of control and DSP-type applications, such as wireless sensor networks requiring local signal processing.

Icyflex-2 is a smaller 16/32 bit RISC processor for control type applications with power consumption as low as 6-microwatts/MHz in 65-nm LP CMOS process.

Icyflex-4, with a scalable architecture, is capable of some control and massive parallelism for computation-intensive DSP-type applications such as audio or video processing. All three processors are available as VHDL soft blocks with multiple parameters (bus widths, stack size, optional blocks) so that only the part of the processor useful for the application is integrated. The processors can be configured at run time to add new addressing modes and new instructions to reduce the number of cycles for individual algorithms. The processors feature up to 36 multiply-and-accumulate units and high-bandwidth buses to registers and memory for maximum throughput per instruction, or clock cycle. The processors are designed for testability and on-chip debug support through a JTAG interface.

Development tools are available, based on the GNU tool suite, compiler, assembler, debugger, cycle accurate instruction set simulator, with a plug-in for the Eclipse IDE. The Icyflex processor cores are available either as IP cores under license, or as part of a low-power SoC design at CSEM.

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