IMFT 25-nm MLC NAND: technology scaling barriers broken

The technical and manufacturing prowess of Intel Micron Flash Technologies (IMFT) is proven once again by the introduction of their latest 25-nm 8-GB (64 Gb), 2-bit/cell MLC (multi-level cell) NAND flash. While most pundits have speculated that NAND has hit the wall, IMFT continued their aggressive path of NAND scaling and may even get one more node at 18 nm. On the scaling front, it's clear that IMFT is following 0.7x scaling every 12-15 months, which translates to almost 0.97x scaling compared with the logic technology time scale.

The IMFT 25-nm die has an impressive foot print of 162 mm^{false true 1 2}, one-sided pad layout, 79-percent memory area efficiency (vs. die area) and is packaged in 48-pin lead-free TSOP. Another significant gain is double the memory capacity compared with the 4-GB (32 Gb) 34-nm 2-bit/cell MLC NAND die at approximately same die size. This may not cut the NAND flash or SSD price by half but it's something the SSD manufacturers would cheer about. The die is divided into two 32-Gb planes used in single or dual-plane operation. The bitline access and page buffers are placed in the center of the die dividing the bitlines into half. This helps reduce the bitline capacitance and improves charging and discharging time.

For the first time, IMFT has successfully fabricated a 2x-nm node 8-GB 2-bit-per cell NAND flash using floating-gate cell technology Click on image to enlarge.

NAND array overhead, (calculated as a ratio of overhead length to the total length of NAND string) stands at 14 percent for the current IMFT 25-nm 66-cell NAND string, compared with 23 percent overhead for the 33-cell NAND string used at 34 nm. That means the voltage controllers have to be dedicated for edge cells and the control circuitry have to work smarter and switch faster. In order to balance between the edge wordline effects and providing a cost-effective die size, the cell 0 and cell 65 are most likely one bit-per cell. The other alternative would have been to use a 67-cell string and use the edge cells as dummy wordlines, which would increase the die size.

IMFT was first to release 3x-nm node followed by their recent announcement of 2x-nm node. IMFT strategy seems to be more toward the node shrink first and then 3-bit-per cell. Samsung and Toshiba slowly but surely are working toward 2x-nm node, while Hynix may announce their 2x-nm node in Q3-10. The choice between 3-bit-per cell (higher density/low cost) and 2-bit-per cell (lower density/more reliable) depends on whether the device is used for portable, cheaper storage (USB) or solid-state drive (SSD) market. Much remains to be seen what happens at the end of the year 2011.