IMFT 25-nm MLC NAND: technology scaling barriers broken

The key for successful product roll out depends on how well the front-end-of-the-line (FEOL) process technologies like immersion lithography, self-aligned-double-patterning (SADP), self-aligned poly process, narrow shallow trench isolation (STI) gap fill, and air-gap isolation are integrated with each other. IMFT have used these technologies to successfully solve the physical, electrical, and reliability scaling challenges. The Process Analysis group at UBM TechInsights has recently analyzed the IMFT's 25-nm device to gain deeper understanding of the process technologies used.

TEM image of the IMFT 25-nm flash array in wordline direction: IMFT takes advantage of the high-aspect-ratio wordlines to create a good gate-to-gate isolation

Topographical SEM image of the IMFT 25-nm flash memory array at gate level: array trench depth is shallower to allow a denser flash array

The extent of immersion-lithography tool usage cannot be known, but our end-of-the-wordline analysis and STI pattern analysis of the IMFT device has shown some interesting spacing patterns that could give useful insight into the lithography and SADP processes. Technically, immersion lithography is the mainstream technology for NAND flash integration for sub-50 nm and is used along with SADP to shrink line widths and avoid overlay issues. Strongly enhanced DP (two exposures + spacer approach) could extend immersion to 21 nm and beyond. Since the extreme ultraviolet lithography (EUVL) tool is not going to be ready till 2012, immersion would continue to fill the gap up to 2x-nm node and beyond.

In the memory array, the STI aspect ratio increased significantly, which made gap fill in the STI difficult. Flowable dielectrics, such as spin on glass (SOG), offer a scalable alternative. So trench filling has also changed to a two-step process requiring a liner followed by a gap fill. One thermal process that is extensively used is high aspect ratio process (HARP) using TEOS/ozone to perform conformal gap fill for aspect ratios greater than 10:1 prior to the SOG fill. Trench depths and spacing are separately optimized for array and periphery, with array trench depth being shallower to allow a denser flash array. Peripheral control transistors used for switching needed better and deeper voltage isolation. Our report details how IMFT made this STI gap fill possible.

To obtain better contact to bitline resistance and reduce process steps, tungsten/N+ poly contacts were replaced by tungsten only at 25-nm node. Further analysis is required to help us understand more on the usage of via zero level, staggered bitline contacts, liner materials and barrier materials.

Parasitic coupling between adjacent cells poses a big problem as the spacing between floating gates shrink, causing a shift in the Vth. To overcome this, IMFT has reduced the gate dimensions and oxide spacer thickness compared with its 34-nm device. The side-wall-to-coupling ratio between CG to FG is reduced by reducing the FG height. Inter-poly dielectric thickness is optimized to keep the coupling ratio high between the CG and FG. The isolation gap fill between the gates is also an important integration challenge to resolve. IMFT solved this problem by using the existing deposition techniques and taking advantage of the high-aspect-ratio wordlines to create a good gate-to-gate isolation.

Finally all these improvements added together, provide a unit cell area of 0.00138 µm^{false true 2 2} per bit-or 0.00275 µm^{false true 2 2} per two bits. That compared with 0.0046 µm^{false true 2 2} per two bits in the IMFT 34-nm device. For the first time, IMFT has successfully fabricated a 2x-nm node 8-GB 2-bit-per cell NAND flash using floating-gate cell technology. They have used the existing semiconductor processes in a cost-effective way to deliver a reliable NAND flash memory. We would probably see some introduction of alternative technologies like charge trap memory, 3D-BiCS, vertical channel, DG-TFT in years 2012- 2013. In the near term, the manufacturing competitiveness, densities offered and the decreasing price will increase the NAND adoption rates.

Ramesh Kuchibhatla is a senior technology analyst responsible for technical and market analysis of semiconductor products at UBM TechInsights. He holds a Master of Engineering Science degree from Queensland University of Technology, Australia.