IBM warns of 'design rule explosion' beyond 22-nm

PORTLAND, Ore.—An IBM researcher warned of "design rule explosion" beyond the 22-nanometer node during a paper presentation earlier this month at the International Symposium on Physical Design (ISPD).

Kevin Nowka, senior manager of VLSI Systems at the IBM Austin Research Lab, described the physical design challenges beyond the 22-nm node, emphasizing that sub-wavelength lithography has made silicon image fidelity a serious challenge.

"Simple technology abstractions that have worked for many generations like rectangular shapes, Boolean design rules, and constant parameters will not suffice to enable us to push designs to the ultimate levels of performance," Nowka said.

Solving "design rule explosion," according to Nowka, involves balancing area against image fidelity by considering the physical design needs at appropriate levels of abstraction, such as within cells. Nowka gave examples of how restricted design rules could reap a three-fold improvement in variability with a small area penalty.

Nowka envisions physical design rules beyond the 22-nm node that are more technology-aware and which make use of pre-analysis and library optimization for improved density and robustness, he said.

IBM described a solution to "design rule explosion" at the 22 nanometer node illustrated in an SRAM chip design.