IBM benchmarks prod microprocessor designers

PORTLAND, Ore.—A new suite of benchmarks released by IBM Research, in cooperation with Intel Research, will likely accelerate the development of robust new clock distribution schemes for next-generation microprocessors, according to the clock network synthesis contest organizers at the International Symposium on Physical Design (ISPD).

The benchmarks were originally developed for ISPD's clock network synthesis design contest, which was won by professor Igor Markov's team from University of Michigan for the second straight year.

"There is a gap between industry and the academic community, and I believe that the research stimulated by this contest can serve an important role in bridging this gap," said Prashant Saxena, ISPD general chair and principal engineer at EDA vendor Synopsys Inc. Used to pick the winners in this year's clock synthesis contest, the high-performance benchmarks will now be used by industry and academic chip designers alike to improve next-generation microprocessors and application-specific integrated circuits (ASICs).

"Microprocessor and high-performance ASIC designs urgently need new technology to build a robust clock network which is tolerant to on-chip variations for 45-nanometer and beyond," said Saxena. "The clock contest was quite revolutionary this year. Real-world industrial practice for high-end designs will very likely be influenced by the techniques used in this contest, which I believe will lead to major new research developments in this field."

IBM Research did most of the heavy lifting in developing the benchmarks for the extremely challenging task set to contestants this year, which was to use the least amount of energy—to extend battery life for a portable device—while still accurately distributing a 2-GHz clock across a microprocessor die with less than 7.5 picoseconds of skew. Twenty teams entered the contest, only 10 of which survived to the finals—a single rule violation disqualified a contestant.

IBM Research evaluated the contestants' entries on eight industrial benchmarks, derived from both IBM and Intel microprocessors and verified by electrical circuit simulation. The benchmarks were made public after the announcement of the contest results, with the aim of pushing clock synthesis research forward.