News & Analysis
CebaTech rolls protocol acceleration subsystems
4/26/2010 9:01 AM EDT
Executing application protocols in FPGA-based hardware with a path to low cost implementation for high-volume applications, the CebaFlex series offloads the central processing unit (CPU), freeing up CPU cycles, which can be used for higher value-add application processing, according to CebaTech (Eatontown, N.J.).
CebaFlex's re-programmability enables OEM customers to rapidly deploy next-generation equipment, independent of the CPU technology lifecycle, CebaTech said. Its in-system upgrade capability enables the after-market addition of new software functionality to the system, boosting performance, according to the company.
CebaFlex production-ready boards meet the reliability and environmental operating standards required by embedded systems equipment, and are used for both prototyping and product realization, CebaTech said. The PCI Express interface enables plug and play connection to standard network and storage chassis, according to the company.
The initial CebaFlex offering supports industry-standard data management functions such as GZIP compression, GUNZIP decompression and AES encryption algorithms, using the company's CebaRIP rapidly tunable intellectual property (IP) core library, CebaTech said. The company added that it also implements custom protocols in CebaFlex subsystems as a full turnkey solution.
CebaFlex uses ANSI C-to-hardware compiler technology to design and tune hardware implementations of both standard and custom protocols to meet the different performance, power and area trade-offs required by different applications, according to CebaTech. Using this technology, customers can have CebaTech compile and offload their ANSI C algorithms onto the hardware platform to produce a customized solution that meets their specific market needs, the company said.


