Integration ignites IC packaging trends

Integration ignites IC packaging trends
Despite a year of lackluster growth, wireless communications customers are still in the driver's seat when it comes to pushing for advanced packaging technologies that play into their requirements for smaller, lighter, more affordable products.

Performance, reliability, and cost have influenced any number of new designs, spawned options such as die stacking or systems-in-a-package (SiP), and pulled test functions into the assembly process in an effort to improve yields and lower manufacturing overhead.

"Packaging continues to become more application-specific, with a number of technology trends gaining momentum that deliver optimal performance at the lowest cost," said Scott Jewler, senior vice president of the Assembly Business Unit at Amkor Technology Inc., Chandler, Ariz.

Advanced packaging also continues to call for new equipment and processes, causing integrated device manufacturers (IDMs) to outsource a greater percentage of their packaging and testing needs to semiconductor assembly and test services (SATS) providers.

The higher margins typically associated with newer packages are expected to drive up revenue for SATS providers 10% to 17% this year, according to analysts' estimates, with most of the growth coming in the second half of this year. In 2002, SATS providers accounted for $8.4 billion of the total $26.7 billion global market for packaging test and assembly.

"We have package proliferation," said Jim Walker, principal analyst for semiconductor packaging and assembly at Gartner Dataquest, San Jose. "Many IDMs don't want to tool and expend capital to build all these newer packages, so they're being outsourced on a higher-percent basis than the older packages."

Hitachi Semiconductor (America) Inc., San Jose, expects to outsource more packaging operations this year "because some existing products aren't efficient for in-house production and some of the new products may not be profitable when produced in-house," said Toshihiko Sato, department manager for the Test & Packaging Technology Division, S&IC, of Hitachi Ltd.

Others, like nonvolatile-memory specialist Silicon Storage Technology Inc. (SST), Sunnyvale, Calif., have already outsourced nearly all of their packaging assembly and test business.

The trend is forcing SATS providers to increase their capital outlay by an average annual rate of 15% to 20% to meet required investments for lead-frame, flip-chip, SiP, and stacked packages as well as in-strip test and fine-pitch assemblies. In some cases, more sophisticated devices have driven the cost of test systems as high as $3.5 million, from about $1.5 million two years ago, according to Ralph Duceour, president and chief executive of Advanced Interconnect Technologies Inc. (AIT), Pleasanton, Calif.

Some of the packaging industry's investments will be spent in the growing China region, although companies are scrutinizing business opportunities and customer demand more closely before moving into the country.

Andy Qin, an analyst at iSuppli Corp. in Guangzhou, China, said the government continues to support the development of a semiconductor market. Packaging revenue represented 80% of China's entire IC industry in 2001, and Qin forecasts 26.2% growth for the country's semiconductor packaging industry in 2003.

Trade-offs

The move to any new package architecture often results in a number of cost and performance trade-offs. The wireless communications industry is trying to reap the best of both worlds by moving to SiP devices, which offer ever higher levels of integration.

Emerging as a standard for wireless handsets, the integration of multiple components inside traditional chip-scale packages meets the real estate and performance requirements of new wireless protocols like 2.5G and 3G.

"Such technologies hold great promise in that they leverage the industry's robust packaging process technology portfolio to enable integration of both active and passive functionality into an IC package without the complexity associated with alternative system-on-chip solutions," said B.J. Han, chief technology officer for Singapore-based ST Assembly Test Services Ltd. (STATS).

Such stacked-die techniques are working their way into a variety of applications, according to Han, including handhelds, consumer electronics, and PCs that require some integration of memory and logic, mixed-signal, or baseband/RF.

"We're seeing system-integrated packaging where people are stacking two or three die in a package," said Frank Ramsay, director of ASIC marketing at Toshiba America Electronic Components Inc., San Jose. Packaging is becoming more complicated, particularly for cell phones, which need flash memory and logic chips in a single package, according to Ramsay.

"It's more cost-effective, if there are high volumes, to put two die in a package rather than make one more-complex die with embedded flash technology," he said.

Some obstacles

Two of the key obstacles with which die stacking has confronted designers are die and wafer handling and the maintenance of thermal levels. This is becoming particularly apparent in the mobile computing industry, where many communications devices are no more than an inch thick and are designed to fit in the palm of your hand.

"When you start stacking silicon, you have to thin the die down, so handling thin die and thin wafers is a challenge--especially for 300mm wafers because they are ground down to 60 to 100 microns," said Gartner Dataquest's Walker. "Plus, as you integrate more functions on the die, it requires closer bond tabs and this requires a new generation of equipment."

Though it has outsourced its package and test operations, SST has developed in-house a Micro Package for flash memory products. Measuring just 4 x 6mm, the Micro Package offers the same 0.5mm contact pitch and pinouts from 1 to 32 Mbits, allowing customers to use the same package for multiple densities of flash.

"We're able to offer a package that is density-independent," said Ben Cheung, product marketing manager for SST's standard memory product group. Volume production of the Micro Package is scheduled for late in the first quarter of this year. The package will be available in either a ball-grid array or land-grid array. Pricing is expected to be comparable to SST's existing BGA packages.

High-power-dissipation BGAs are also gaining momentum, according to Marcos Karnezos, chief technology officer for ChipPAC Inc., Fremont, Calif. In this area, the trend is to go from a cavity-down BGA to a cavity-up BGA, which offers lower cost and greater flexibility in die size and pin count.

Though the cavity-down method has higher power dissipation, ChipPAC has developed technologies to bridge the gap between the two. Over the past 18 months, ChipPAC has seen the package take off quickly in gaming and laptop applications, Karnezos said.

Changing test requirements

As the industry moves to more tightly integrated packaging, a change is occurring in terms of testing procedures. Where once test was performed after assembly, there is a growing tendency to test packages during the assembly process to save time and money.

Specifically, testing is often conducted following the attachment of the passive components but before higher-value silicon is soldered to the substrate. "This means that any defects up to that point can be removed, before the silicon is attached, and subsequently thrown away because of a faulty passive," said STATS' Han.

Moreover, provided that the substrate is designed for test access, assemblers are sometimes able to forgo the use of fully functional automated test equipment (ATE) in favor of lower cost options, according to Han.

Some logic and mixed-signal ATE are capable of economically testing many devices in parallel, which allows manufacturers to test some packages before singulation. Testing in strip form may be the best or even the only way to handle very small packages at final test because of handling difficulties, Han said.

In fact, in many cases, silicon and packaging are being developed together at the outset of a new design because the package can compromise silicon functionality, speed, and reliability as well as create thermal and cost issues, Gartner Dataquest's Walker said.

This is especially true in high-end chips with 5, 10, and 15 million gates where designs are so demanding that packaging can no longer come as an afterthought.

While wireless companies may be driving the demand for stacked die and SiPs, other end markets are exerting an influence on the development of new package styles.

For ASICs, FPGAs, and ASSPs where the number of I/Os can easily climb into the thousands, many customers are moving to flip-chip packaging for optimal electrical performance. Networking applications that require high-speed ASICs, for example, can benefit from SiP by reducing trace lengths between the logic and memory devices, according to Amkor's Jewler.

Typically, flip-chip packaging can be used for advanced ASICs, DSPs, memory, microprocessors/controllers, PC chipsets, and gate arrays, while wafer-level CSPs are used in portable products such as mobile phones, Web pads, and digital cameras. In fact, of all applications, it is the PC that may "facilitate the wide adoption of flip-chip for other applications as the supply chain for high-density substrates matures," Jewler said.

While many high-speed, high-density devices with 1,500 or more I/Os are moving to flip-chip packages, wirebonding isn't expected to go away any time soon, given that the primary manufacturers of wirebond equipment continue to improve their fine-pitch wire-bond capabilities, said AIT's Duceour.

As a competing technology to wirebonding, AIT recently licensed a pillar-bumped flip-chip technology from Advanpack Solutions Pte. Ltd., headquartered in Singapore. The technology is said to provide better electrical and thermal enhancement and a lower profile than today's wirebond technology and is available in a lead-free format.

Cost drivers

Cost is clearly a primary concern for all package types and presents a challenge in terms of process development, materials selection, and design in many high-volume manufacturing environments, Walker said.

Packaging costs on average represent about 15% to 17% of the total cost of an IC. In general, the lower the I/O count, the less it costs to manufacture a given die and the more packaging contributes to the overall cost of the device.

Packaging costs are also climbing because they have to meet new silicon requirements for fine pitch, finer bond pads, thinner form factors, and a whole new set of cost and performance characteristics associated with the electronics industry's drive toward lead-free components.

Set against that backdrop, there is a major move under way to shift away from small-outline packages (SOICs) to quad-flatpack no-lead (QFN) packages, particularly in the latest generation of cellular phones, PDAs, and other wireless products. Despite the fact that QFN packages are relatively new and as such come at a premium, the higher cost is expected to disappear under a fast production ramp, according to Walker.

Carl Roberts, fellow and director of advanced packaging at Analog Devices Inc., Norwood, Mass., said that lead-frame chip-scale packaging (LFCSP), commonly called QFN, QLP, or MLP, will substantially displace the leaded SOIC family over the next three to five years. Roberts said the biggest immediate advantage is size. A typical product packaged in an LFCSP can be accommodated in a package 65% to 70% percent smaller than an SOIC.