Los Alamos, Tachyon to develop 3D chips based on wafer-stacking process

Los Alamos, Tachyon to develop 3D chips based on wafer-stacking process
NAPERVILLE, Ill. -- Tachyon Semiconductor Inc. and Los Alamos National Laboratories announced an alliance to develop system-on-a-chip (SoC) designs, based on Tachyon's wafer-stacking process technology.

The two entities are also looking to define the production of three-dimensional (3D) integrated devices, based on Tachyon's process. The company's wafer-stacking process allows different circuitry elements to be built on several separate wafers--each of which is optimized for specific components, according to Naperville-based Tachyon.

The finished wafers in the process are stacked, bonded, and interconnected with thousands of through-silicon "vias" to create an integrated device.

Tachyon has been sub-contracted by the University of California and Timension Inc. to adapt its technology for use in devices being developed by the Los Alamos National Labs.

Under the agreement, Tachyon will produce a report detailing the production of an SoC device with separate layers for the microprocessor, flash memory, FPGA, and DRAM.