Tezzaron rolls out 'PSiRAM' memory technology

The technology, dubbed PSiRAM, is said to enable one of the world's fastest memory devices for system-on-a-chip (SOC) applications. A PSiRAM prototype device boasts 1.3-ns latencies, 1-ns cycle times, and an overall throughput of 2 gigabits-per-second on each pin.

The PSiRAM prototype was built in a 90-nm process, producing memory cells measuring only 0.59-square-microns each. Tezzaron intends to license PSiRAM technology for use in SoC applications.

The underlying technology for this device is a patented 3-transistor cell, which senses changes in electrical current rather than measuring electrical voltage, according to Tezzaron. The Naperville-based fabless company specializes in three-dimensional packaging technology, but it has apparently thrown its hat in the memory market.

"Our PSiRAM is pseudo static," said Bob Patti, chief technology officer of the company. "So it requires refresh, but reads are nondestructive, so a read does not necessary imply that a refresh is required or done. The three-transistor cell provides independent read and write paths and has a gain transistor on the storage capacitor," Patti said.

The company has big plans with the technology. "We will provide two different versions of the part to the market. One will have completely hidden refresh, and thus appear as a standard SRAM," he said. "The other will require user refresh much like DRAM does today. The DRAM version will run faster than the SRAM version. The SRAM part would have a latency of [around] 1.8-ns instead of 1.3-ns."

Tezzaron has devised a prototype of the PSiRAM, which based on a quad data rate (QDR) architecture. The 32-megabit prototype device is organized in a 2-Mbit x 16 configuration.

The device is designed to run at 1.2 Volts, but it has been tested at 0.8 V. At the lower voltage, the device exhibits speeds in excess of 400-MHz and power dissipation of less than 0.125 Watts.

Tezzaron plans full production of PSiRAM chips next year. A 130-nm version is slated for the first half of 2004, followed by a 90-nm version late next year.