Intel targets Oregon fab for volume 65-, 45-nm chips

SANTA CLARA, Calif.--Intel Corp. today (November 24, 2003) disclosed the details of its 65-nm process, which is an 8-layer technology equipped with copper interconnects, low-k dielectrics, strained-silicon, and "hard" or alternating phase-shift photomasks.

During a briefing with press and analysts, Intel also disclosed that its 300-mm development fab in Oregon will become the initial high-volume plant for both its 65- and 45-nm process technologies.

The 65-nm process technology announcement was expected. Earlier today, the process was disclosed on a Web site called Channel Times (see November 24 story).

As reported, Intel has built 4-megabit SRAM chips using 65-nm technology. The memory cell of the device measures 0.57um2. Each SRAM memory cell has six transistors--10 million of these transistors would fit in one square millimeter, according to the Santa Clara-based chip giant.

The company's 65-nm process, dubbed P1264, is expected to be deployed on 300-mm wafers, with production due in 2005, said Mark Bohr, Intel Senior Fellow and director of process architecture and integration. "By 2005, we expect to be the first company to have a 65-nm process in manufacturing," Bohr said.

The 65-nm semiconductor devices were manufactured at Intel's so-called D1D 300-mm development fab in Hillsboro, Ore. "D1D will be the first high-volume manufacturing fab for the 65-nm technology," Bohr said.

The D1D fab is also targeted for initial high-volume production at the 45-nm node, which is slated for 2007. The fab will run both 65- and 45-nm devices simultaneously, he said during the conference call.

It will also enable the company to sustain Moore's Law. "This accomplishment puts Intel's 65-nm technology on a fast track to extend our 15 year record of ramping production on a new process generation every two years. In fact, only 20 months have elapsed since we disclosed achievement of fully functional SRAMs on our 90-nm process, which is now ramping," said Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group, in a statement.

"The 65 nm process will enable us to make better products at lower cost, as we continue to innovate and extend Moore's Law," he added.

By year's end, Intel is expected to ramp up its 90-nm process. Its first 90-nm design, codenamed Prescott, is a processor based on the Pentium 4 architecture. Intel is also expected to develop processors in the first phases of its 65-nm process, the company said.

Intel's new 65-nm process will feature transistors measuring 35-nm in gate length. The process consists of strained-silicon, copper interconnects and a low-k dielectric material, he said.

Intel has integrated a second-generation version of its high-performance strained silicon into this process. It deployed its first strained-silicon process at the 90-nm node. Strained silicon provides higher drive current, increasing the speed of the transistors with only a two percent increase in manufacturing cost.

The process also integrates eight copper interconnect layers and uses a low-k dielectric material that increases the signal speed inside the chip and reduces chip power consumption. Like its 90-nm process, the 65-nm technology makes use of a carbon-doped oxide technology, built around chemical vapor deposition (CVD) tools. The k-value is "less than 3.0," according to Bohr.

As expected, Intel has extended its 193-nm scanners for the 65-nm node. Earlier this year, the company removed 157-nm scanners from its roadmap for the 65-nm node, due to technical problems. The company expects to reuse the 193- and 248-nm lithography equipment currently used on its 90-nm process, as well as adding some upgraded 193-nm tools.

Intel will use 193-nm "dry" tools for the 65-nm node, as opposed to the newfangled immersion technologies, he said. "Immersion is one of the options at Intel," he said. "It's not the leading option."

The company is also moving towards "hard" or alternating phase shift mask (APSM) technologies for the 65-nm node. "The 65-nm node is the first time we're confirming (the deployment) of APSM," he said.