News & Analysis
Six 3D designs precede 90% power-saving claims from Tezzaron
Peter Clarke
12/23/2004 7:42 AM EST
Tezzaron (Naperville, Illnois) has developed a design style that partitions a design into two or more ICs and place, say memory on one die and a microcontroller on another, but with vias and interconnect in corresponding positions on the two die to create short connections when the die are stacked together during wafer processing. The company, with connections to and support from the Singapore Institute of Microelectronics, calls its technology FaStack.
The vertical connections are shorter than 2D horizontal traces by a factor of 100 to 1000, so FaStack devices draw only 1/3 the current and consume 1/10 the power of their 2D counterparts, generating far less heat, the company said, without referencing a particular circuit.
Earlier in December 2004 Tezzaron itroducted a "super-8051" using its 3D technology.
In describing the general benefits of the FaStack system Tezzaron said flexibility of design enables 3D sensors with 100% array efficiency, compared too 40 to 50 percent array efficiency in 2D, 3D memories with two nanosecond latencies versus 25 to 40-ns in 2D, and 3D processors that operate three to ten times faster than their 2D counterparts.
A more familiar FaStack design flexibility, and one already pursued in in conventional multi-chip packaging, is the ability to partition according to process requirements; for example, placing analog and digital circuitry on separate die and different layers in the stack can avoid process compromises and increase the quality of the circuits.
Tezzaron's wafer stacking can also accommodate differing substrates, integrating, for example, silicon and silicon-germanium in a 3D component. Such heterogeneous integration of substrates would be very good news for Wi-Fi, Bluetooth, and other RF devices, according to Subhash Gupta, managing director, of Tezzaron.



